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yosys.git
2014-09-01
Clifford Wolf
Added "techmap -autoproc"
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2014-09-01
Clifford Wolf
Fixes in old SAT example.ys
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2014-09-01
Clifford Wolf
Moved "share" and "wreduce" to passes/opt/
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2014-09-01
Clifford Wolf
Using std::vector<RTLIL::State> instead of RTLIL::Const...
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2014-08-31
Clifford Wolf
Added eval testing to test_cell
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2014-08-31
Clifford Wolf
Fixed return size of const_*() eval functions
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2014-08-31
Clifford Wolf
Added RTLIL::Const::size()
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2014-08-31
Clifford Wolf
Added eval model for $lut cells
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2014-08-31
Clifford Wolf
Typo fixes in cell->*Param() API
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2014-08-31
Clifford Wolf
Added $lut support in test_cell, techmap, satgen
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2014-08-30
Clifford Wolf
Added design->scratchpad
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2014-08-30
Clifford Wolf
Added $alu cell type
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2014-08-30
Clifford Wolf
Added autotest -e (do not use -noexpr on write_verilog)
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2014-08-30
Clifford Wolf
Improved write address decoder generation memory_map
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2014-08-30
Clifford Wolf
Fixed module->addPmux()
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2014-08-30
Clifford Wolf
Using worker class in memory_map
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2014-08-30
Clifford Wolf
Replaced $__alu CO/CS outputs with full-width CO output
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2014-08-30
Clifford Wolf
Don't change existing binary FSM encoding if it is...
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2014-08-30
Clifford Wolf
Using $pmux info in fsm_extract to optimize transition...
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2014-08-30
Clifford Wolf
Improved handling of $pmux cells in fsm_extract
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2014-08-27
Clifford Wolf
Fixed inserting of Q-inverters in dfflibmap
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2014-08-27
Clifford Wolf
Fixed printing of multi-line Makefile.conf
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2014-08-26
Clifford Wolf
Implemented "rename -enumerate -pattern"
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2014-08-26
Clifford Wolf
Print Makefile.conf as make info message
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2014-08-25
Clifford Wolf
Checking for valid CONFIG value in Makefile
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2014-08-24
Clifford Wolf
Optimize shift ops with constant rhs in opt_const
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2014-08-24
Clifford Wolf
Added some additional log messages to opt_const
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2014-08-24
Clifford Wolf
Added is_signed argument to SigSpec.as_int() and Const...
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2014-08-24
Clifford Wolf
azonenberg: Make dump_vcd save model when temporal...
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2014-08-23
Clifford Wolf
Only call proc_share_dirname() in techmap when necessary
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2014-08-23
Clifford Wolf
Removed compatbility.{h,cc}: Not using open_memstream...
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2014-08-23
Clifford Wolf
Changed frontend-api from FILE to std::istream
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2014-08-23
Clifford Wolf
Changed backend-api from FILE to std::ostream
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2014-08-22
Clifford Wolf
Added "stat -width"
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2014-08-22
Clifford Wolf
Added emscripten (emcc) support to build system and...
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2014-08-22
Clifford Wolf
Added DPI-C documentation to README file
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2014-08-22
Clifford Wolf
Added support for non-standard <plugin>:<c_name> DPI...
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2014-08-22
Clifford Wolf
Archibald Rust and Clifford Wolf: ffi-based dpi_call()
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2014-08-22
Clifford Wolf
Added "plugin" command
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2014-08-22
Clifford Wolf
Updated ABC to 4d547a5e065b
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2014-08-21
Clifford Wolf
Cosmetic changes to FSM tests
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2014-08-21
Clifford Wolf
Fixed small memory leak in ast simplify
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2014-08-21
Clifford Wolf
Added support for DPI function with different names...
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2014-08-21
Clifford Wolf
Added AstNode::asInt()
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2014-08-21
Clifford Wolf
Fixed memory leak in DPI function calls
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2014-08-21
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-08-21
Clifford Wolf
Added Verilog/AST support for DPI functions (dpi_call...
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2014-08-21
Clifford Wolf
Added support for global tasks and functions
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2014-08-19
Clifford Wolf
Added mod->addGate() methods for new gate types
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2014-08-18
Clifford Wolf
Using "via_celltype" in $mul carry-save-acc implementation
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2014-08-18
Clifford Wolf
Added "via_celltype" attribute on task/func
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2014-08-17
Clifford Wolf
Performance fix for new $__lcu techmap rule
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2014-08-17
Clifford Wolf
Replaced recursive lcu scheme with bk adder
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2014-08-17
Clifford Wolf
Added const folding of AST_CASE to AST simplifier
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2014-08-17
Clifford Wolf
Fixed proc_{self,share}_dirname error handling
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2014-08-17
Clifford Wolf
Makefile fixes
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2014-08-17
Clifford Wolf
Improved AST ProcessGenerator performance
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2014-08-17
Clifford Wolf
Improved sig.remove2() performance
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2014-08-16
Clifford Wolf
Use stackmap<> in AST ProcessGenerator
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2014-08-16
Clifford Wolf
Added stackmap<> container
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2014-08-16
Clifford Wolf
Renamed toposort.h to utils.h
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2014-08-16
Clifford Wolf
Added module->uniquify()
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2014-08-16
Clifford Wolf
Fixed AOI/OAI expr handling in verilog backend
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2014-08-16
Clifford Wolf
Multiply using a carry-save accumulator
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2014-08-16
Clifford Wolf
Added "test_cell -s <seed>"
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2014-08-16
Clifford Wolf
AST ProcessGenerator: replaced subst_*_{from,to} with...
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2014-08-16
Clifford Wolf
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_...
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2014-08-16
Clifford Wolf
Added CellTypes::cell_evaluable()
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2014-08-16
Clifford Wolf
Changes in techmap $__alu interface
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2014-08-16
Clifford Wolf
Added "opt -fast"
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2014-08-16
Clifford Wolf
Added log_spacer()
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2014-08-15
Clifford Wolf
Bugfix in iopadmap
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2014-08-15
Clifford Wolf
Renamed $lut ports to follow A-Y naming scheme
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2014-08-15
Clifford Wolf
Renamed $_INV_ cell type to $_NOT_
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2014-08-15
Clifford Wolf
Removed old doc references to $safe_pmux
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2014-08-15
Clifford Wolf
More idstring sort_by_* helpers and fixed tpl ordering...
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2014-08-15
Clifford Wolf
Added Frontend "+/" filename syntax for files from...
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2014-08-15
Clifford Wolf
document "techmap -map %<design-name>"
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2014-08-14
Clifford Wolf
Fixed bug in "read_verilog -ignore_redef"
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2014-08-14
Clifford Wolf
Added RTLIL::SigSpec::to_sigbit_map()
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2014-08-14
Clifford Wolf
Changed the AST genWidthRTLIL subst interface to use...
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2014-08-14
Clifford Wolf
Added sig.{replace,remove,extract} variants for std...
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2014-08-14
Clifford Wolf
Fixed line numbers when using here-doc macros
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2014-08-14
Clifford Wolf
Fixed handling of task outputs
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2014-08-14
Clifford Wolf
Simplified $__arraymul techmap rule
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2014-08-14
Clifford Wolf
Added module->ports
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2014-08-14
Clifford Wolf
Refactoring of CellType class
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2014-08-14
Clifford Wolf
RIP $safe_pmux
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2014-08-14
Clifford Wolf
Some improvements in FSM mapping and recoding
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2014-08-14
Clifford Wolf
Added "abc -D" for setting delay target
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2014-08-14
Clifford Wolf
Updated ABC to 4935c2b946de
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2014-08-13
Clifford Wolf
Added techmap support for actual lookahead carry unit
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2014-08-13
Clifford Wolf
Preparations for lookahead ALU support in techmap.v
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2014-08-13
Clifford Wolf
Filter ANSI escape sequences from ABC output
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2014-08-13
Clifford Wolf
New interface for $__alu in techmap.v
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2014-08-13
Clifford Wolf
Added support for non-standard """ macro bodies
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2014-08-12
Clifford Wolf
Fixed handling of constant-true branches in proc_clean
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2014-08-12
Clifford Wolf
Added test_verific mode to tests/fsm/generate.py
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2014-08-12
Clifford Wolf
Fixed SigBit(RTLIL::Wire *wire) constructor
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2014-08-12
Clifford Wolf
Fixed building verific bindings
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