| 2018-12-15 |
whitequark | Rename fhdl→hdl, genlib→lib. |
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| 2018-12-15 |
whitequark | Move star imports to make `from nmigen import *` usable. |
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| 2018-12-15 |
whitequark | doc: fix some Markdown awkwardness. |
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| 2018-12-15 |
whitequark | doc: update COMPAT_SUMMARY to reflect actual status. |
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| 2018-12-15 |
whitequark | Determine Migen's API surface and document compatibilit... |
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| 2018-12-15 |
whitequark | pyback.sim: test Slice, Cat, Repl. |
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| 2018-12-15 |
whitequark | fhdl.ast, back.pysim: implement shifts. |
commit | commitdiff | tree |
| 2018-12-15 |
whitequark | fhdl.ast: refactor Operator.shape(). NFC. |
commit | commitdiff | tree |
| 2018-12-15 |
whitequark | Consistently use '{!r}' in and only in TypeError messages. |
commit | commitdiff | tree |
| 2018-12-15 |
whitequark | fhdl.ir: test iter_comb(), iter_sync() and iter_signals(). |
commit | commitdiff | tree |
| 2018-12-15 |
whitequark | fhdl.ir: fix incorrect uses of positive to say non... |
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| 2018-12-15 |
whitequark | compat.fhdl.structure: handle If/Elif with multi-bit... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | compat.fhdl.module: allow adding native submodules... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | Fix deprecations in Python 3.7. |
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| 2018-12-14 |
whitequark | back.pysim: preserve process locations through add_sync... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | fhdl.ast: clean up stub error messages. NFC. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | fhdl.ir: automatically flatten hierarchy to resolve... |
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| 2018-12-14 |
whitequark | fhdl.ir: Fragment.{drive→add_driver} |
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| 2018-12-14 |
whitequark | back.pysim: count delta cycles separately to avoid... |
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| 2018-12-14 |
whitequark | back.pysim: simplify. |
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| 2018-12-14 |
whitequark | back.pysim: revert 70ebc6f2. |
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| 2018-12-14 |
whitequark | back.pysim: fix implicit boolean conversion. |
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| 2018-12-14 |
whitequark | back.pysim: squash one level of hierarchy. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: implement blocking assignment semantics... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: undriven sync signals should return to... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: in simulator sync processes, start by waiti... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: make initial phase configurable. |
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| 2018-12-14 |
whitequark | compat.sim: match clock period. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | compat: add run_simulation shim. |
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| 2018-12-14 |
whitequark | pysim.back: fix add_sync_process wrapper to handle... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | compat.fhdl.module: fix specials. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | compat: add fhdl.specials.TSTriple shim. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | genlib.io: import TSTriple from Migen. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | fhdl.ast: fix Switch with constant test. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | compat: add genlib.cdc.MultiReg shim. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | compat.fhdl.module: update deprecation messages. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: Simulator({gtkw_signals→traces}=). |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: better naming. NFC. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | Travis: install pyvcd. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: implement most operators and add tests. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: close .vcd/.gtkw files on context manager... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: show more legible names for processes in... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: throw exceptions back at processes. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: add gtkw traces even more robustly. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: accept (and evaluate) generator functions. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: skip VCD signal population if VCD is not... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: allow processes to evaluate expressions. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | fhdl.ir: oops, we defined DomainError twice. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: more general clean-up. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: general clean-up. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: accept any valid assignments from processes. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: robustly retrieve vcd names for clk/rst... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | fhdl.xfrm: implement DomainLowerer. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: undriven comb signals should return to... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | ast, back.pysim: allow specifying user-defined decoders... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: fix completely broken codegen for Switch. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: raise an exception if delta cycles blow... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: if requested, write a gtkw file with a... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: explain how delta cycles work. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: delay clock processes by one half period. |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: implement "sync processes", like migen... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: allow suspending processes until a tick... |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | back.pysim: use bare ints for signal values (-5% runtime). |
commit | commitdiff | tree |
| 2018-12-14 |
whitequark | setup: add missing import. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | back.pysim: collect handlers before running (-5% runtime). |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | back.pysim: allow multiple registered handlers per... |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | back.pysim: fix handling of process termination. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | back.pysim: new simulator backend (WIP). |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.cd: rename ClockDomain signals together with domain. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.ir: move Fragment prepare logic from back.rtlil. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | back.verilog: remove debug code. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.ir: record port direction explicitly. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | compat.genlib.fsm: import/wrap Migen code. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.ir: a subfragment's input that we don't drive... |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl, back: trace and emit source locations of values. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | back.rtlil: never give subfragment cells names starting... |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.ir: don't crash propagataing ports in empty fragments. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.ir: implement clock domain propagation. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.ir: remove iter_domains(). |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl: cd_name→domain. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.cd: add tests. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.xfrm: implement DomainRenamer. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.xfrm: add test for ControlInserter with subfragments. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.xfrm: add tests for ResetInserter, CEInserter. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.ir: add tests for port propagation. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | Set up Travis CI. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | Add LICENSE. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | setup: check Python version. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.dsl: add tests for lowering. 99% branch coverage. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.cd: rename ClockDomain.{reset→rst}. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.dsl: add tests for submodules. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.dsl: use less error-prone Switch/Case two-level... |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.ast: fix Switch._?hs_signals() for switch without... |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | back.verilog: detect undriven public wires using Yosys. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | back.rtlil: fix swapped operands in sync assign. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | back.rtlil: explain logic for CD reset insertion. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | back.rtlil: explicitly set the top module. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | fhdl.ir: explain how port enumeration works. |
commit | commitdiff | tree |
| 2018-12-13 |
whitequark | back.rtlil: explain how RTLIL conversion works. |
commit | commitdiff | tree |
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