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yosys.git
2018-10-17
Clifford Wolf
Merge pull request #660 from tklam/parse-liberty-detect...
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2018-10-17
Clifford Wolf
Merge pull request #663 from aman-goel/master
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2018-10-17
Clifford Wolf
Merge pull request #658 from daveshah1/ecp5_bram
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2018-10-17
Clifford Wolf
Merge pull request #641 from tklam/master
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2018-10-17
Clifford Wolf
Merge pull request #638 from udif/pr_reg_wire_error
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2018-10-16
Clifford Wolf
We have 2018 now
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2018-10-16
Clifford Wolf
After release is before release
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2018-10-16
Clifford Wolf
Merge branch 'yosys-0.8-rc'
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2018-10-16
Clifford Wolf
Yosys 0.8
yosys-0.8
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2018-10-16
Clifford Wolf
Update command reference manual
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2018-10-16
David Shah
ecp5: Disable LSR inversion
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2018-10-15
Aman Goel
Minor update
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2018-10-13
argama
detect ff/latch before processing other nodes
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2018-10-13
tklam
stop check_signal_in_fanout from traversing FFs
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2018-10-13
tklam
stop check_signal_in_fanout from traversing FFs
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2018-10-13
tklam
Merge branch 'master' of https://github.com/YosysHQ...
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2018-10-12
David Shah
BRAM improvements
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2018-10-10
David Shah
ecp5: Adding BRAM maps for all size options
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2018-10-10
David Shah
ecp5: First BRAM type maps successfully
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2018-10-10
David Shah
ecp5: Script for BRAM IO connections
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2018-10-09
David Shah
ecp5: Adding BRAM initialisation and config
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2018-10-07
Clifford Wolf
Improve Verific importer blackbox handling
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2018-10-05
David Shah
ecp5: Add blackbox for DP16KD
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2018-10-05
Clifford Wolf
Merge pull request #651 from ARandomOWL/stdcells_fix
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2018-10-05
Clifford Wolf
Add "write_edif -attrprop"
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2018-10-05
Clifford Wolf
Merge pull request #654 from mithro/patch-1
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2018-10-05
Clifford Wolf
Fix compiler warning in verific.cc
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2018-10-05
Tim Ansell
Fix misspelling in issue_template.md
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2018-10-04
Adrian Wheeldon
Fix IdString M in setup_stdcells()
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2018-10-04
Clifford Wolf
Add inout ports to cells_xtra.v
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2018-10-04
Clifford Wolf
Merge pull request #650 from mithro/patch-1
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2018-10-03
Tim Ansell
xilinx: Adding missing inout IO port to IOBUF
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2018-10-03
tklam
Merge branch 'master' of https://github.com/YosysHQ...
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2018-10-02
Clifford Wolf
Merge pull request #645 from daveshah1/ecp5_dram_fix
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2018-10-02
Clifford Wolf
Merge pull request #646 from tomverbeure/issue594
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2018-10-02
Tom Verbeure
Fix for issue 594.
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2018-10-01
Aman Goel
Update to .smv backend
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2018-10-01
Dan Gisselquist
Add read_verilog $changed support
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2018-10-01
David Shah
ecp5: Don't map ROMs to DRAM
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2018-10-01
Aman Goel
Merge pull request #4 from YosysHQ/master
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2018-09-30
Clifford Wolf
Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
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2018-09-30
Clifford Wolf
Fix handling of $past 2nd argument in read_verilog
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2018-09-28
Clifford Wolf
Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
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2018-09-28
Clifford Wolf
Update to v2 YosysVS template
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2018-09-26
tklam
fix bug: pass by reference
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2018-09-26
TK Lam
Fix issue #639
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2018-09-24
Udi Finkelstein
Fixed issue #630 by fixing a minor typo in the previous...
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2018-09-24
Clifford Wolf
Add "read_verilog -noassert -noassume -assert-assumes"
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2018-09-23
Clifford Wolf
Added support for ommited "parameter" in Verilog-2001...
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2018-09-23
Clifford Wolf
Merge branch 'master' of https://github.com/mmicko...
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2018-09-23
Clifford Wolf
Update CHANGELOG
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2018-09-21
Miodrag Milanovic
added prefix to FDirection constants, fixing windows...
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2018-09-21
Clifford Wolf
Update CHANGLELOG
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2018-09-21
Clifford Wolf
Update Changelog
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2018-09-19
Clifford Wolf
Merge pull request #633 from mmicko/master
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2018-09-19
Clifford Wolf
Merge pull request #631 from acw1251/master
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2018-09-19
Miodrag Milanovic
Fix Cygwin build and document needed packages
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2018-09-18
acw1251
Fixed typo in "verilog_write" help message
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-09-17
Udi Finkelstein
Fixed remaining cases where we check fo wire reg/wire...
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2018-09-14
Clifford Wolf
Merge pull request #625 from aman-goel/master
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2018-09-14
Clifford Wolf
Merge pull request #627 from acw1251/master
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2018-09-12
acw1251
Fixed minor typo in "sim" help message
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2018-09-11
Aman Goel
Minor revision to -expose in setundef pass
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2018-09-10
Clifford Wolf
Add iCE40 SB_SPRAM256KA simulation model
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2018-09-05
Clifford Wolf
Add $lut support to Verilog back-end
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2018-09-04
Clifford Wolf
Add "verific -L <int>" option
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2018-08-30
Clifford Wolf
Add "make ystests"
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2018-08-28
Miodrag Milanović
Add GCC to osx deps (#620)
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2018-08-28
Clifford Wolf
Merge pull request #619 from mmicko/master
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2018-08-28
Miodrag Milanovic
Remove mercurial, since it is not needed anymore
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2018-08-28
Clifford Wolf
Merge pull request #618 from ucb-bar/firrtl+modules...
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2018-08-27
Jim Lawson
Merge branch 'master' into firrtl+modules+shiftfixes
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2018-08-27
Jim Lawson
Remove unused functions.
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2018-08-27
Jim Lawson
Merge pull request #3 from YosysHQ/master
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2018-08-27
Clifford Wolf
Add "make coverage"
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2018-08-27
Clifford Wolf
Add ENABLE_GCOV build option
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2018-08-25
Clifford Wolf
Merge pull request #617 from mmicko/master
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2018-08-25
Miodrag Milanovic
static link flag on main executable
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2018-08-23
Jim Lawson
Add support for module instances.
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2018-08-23
Clifford Wolf
Merge pull request #610 from udif/udif_specify_round2
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2018-08-23
Clifford Wolf
Merge pull request #614 from udif/pr_disable_dump_ptr
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2018-08-23
Udi Finkelstein
Added -no_dump_ptr flag for AST dump options in 'read_v...
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-22
Clifford Wolf
Add "verific -work" help message
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2018-08-22
Clifford Wolf
Add Verific -work parameter
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2018-08-20
Udi Finkelstein
Fixed all known specify/endspecify issues, without...
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2018-08-19
Udi Finkelstein
Yosys can now parse https://github.com/verilog-to-routi...
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2018-08-19
Clifford Wolf
Merge pull request #606 from cr1901/show-win
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2018-08-18
Clifford Wolf
Merge pull request #608 from mmicko/master
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2018-08-18
Miodrag Milanovic
no -fPIC for any static build
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2018-08-18
Miodrag Milanovic
respect DISABLE_ABC_THREADS if used
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2018-08-18
Miodrag Milanovic
Enable propagating ARCHFLAGS
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2018-08-18
Miodrag Milanovic
Added option to disable -fPIC on unsupported platforms
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2018-08-18
Miodrag Milanovic
Added gcc-static for easier cross compilation
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2018-08-18
Clifford Wolf
Merge pull request #575 from aman-goel/master
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2018-08-18
Aman Goel
Revision to expose option in setundef pass
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-16
Clifford Wolf
Add "verific -set-<severity> <msg_id>.."
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2018-08-16
Clifford Wolf
Verific workaround for VIPER ticket 13851
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