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yosys.git
2019-09-29
Eddie Hung
Merge pull request #1359 from YosysHQ/xc7dsp
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2019-09-29
Miodrag Milanović
Merge pull request #1413 from YosysHQ/mmicko/backend_bi...
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2019-09-29
Clifford Wolf
Merge pull request #1411 from aman-goel/YosysHQ-master
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2019-09-28
Miodrag Milanovic
Add aiger and protobuf backends binary support
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2019-09-28
Miodrag Milanovic
Support binary files for backends, fixes #1407
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2019-09-28
Eddie Hung
Fix box name
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2019-09-27
Eddie Hung
Re-order
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2019-09-27
Eddie Hung
Missing (* mul2dsp *) for sliceB
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2019-09-27
Eddie Hung
Ooops AREG and BREG to default to -1
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2019-09-27
Aman Goel
Corrects btor2 backend
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2019-09-27
Marcin Kościelnicki
Fix _TECHMAP_REMOVEINIT_ handling.
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2019-09-27
Aman Goel
Merge pull request #7 from YosysHQ/master
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2019-09-27
Miodrag Milanović
Merge pull request #1409 from YosysHQ/mmicko/fix_getopt...
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2019-09-27
Miodrag Milanovic
Change order of parameters, to work on other os
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2019-09-27
Clifford Wolf
Merge pull request #1404 from YosysHQ/fix_gzip_macos
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2019-09-26
Eddie Hung
Update doc with max cascade chain of 20
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2019-09-26
Eddie Hung
Do not always zero out C (e.g. during cascade breaks)
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2019-09-26
Eddie Hung
Update doc
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2019-09-26
Eddie Hung
Zero out ports
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2019-09-26
Eddie Hung
xilinx_dsp_cascade to also cascade AREG and BREG
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2019-09-26
Eddie Hung
Try recursive pmgen for P cascade
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2019-09-26
Eddie Hung
Missing an '&'
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2019-09-26
Eddie Hung
Combine 'flatten' & 'coarse' labels in synth_ecp5 so...
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2019-09-26
Miodrag Milanovic
Make read/write gzip files on macos works, fixes #1357
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2019-09-26
Eddie Hung
Typo
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2019-09-26
Eddie Hung
CREG to check for \keep
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2019-09-26
Eddie Hung
Remove newline
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2019-09-26
Eddie Hung
select once
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2019-09-26
Eddie Hung
Stop trying to be too smart by prematurely optimising
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2019-09-26
Eddie Hung
mul2dsp.v slice names
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2019-09-26
Eddie Hung
Do not die if DSP48E1.P has no users (would otherwise...
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2019-09-26
Eddie Hung
Reject if (* init *) present
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2019-09-26
Eddie Hung
Remove unnecessary check for A_SIGNED != B_SIGNED;...
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2019-09-26
Eddie Hung
Revert "Remove _TECHMAP_CELLTYPE_ check since all ...
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2019-09-26
Eddie Hung
Revert "No need for $__mul anymore?"
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2019-09-26
Eddie Hung
Rework xilinx_dsp postAdd for new wreduce call
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2019-09-26
Eddie Hung
Only wreduce on t:$add
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2019-09-25
Eddie Hung
Remove _TECHMAP_CELLTYPE_ check since all $mul
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2019-09-25
Eddie Hung
Fix memory issue since SigSpec& could be invalidated
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2019-09-25
Eddie Hung
Merge pull request #1401 from SergeyDegtyar/SergeyDegty...
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2019-09-25
Eddie Hung
No need for $__mul anymore?
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2019-09-25
Eddie Hung
unextend only used in init
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2019-09-25
Eddie Hung
Call 'wreduce' after mul2dsp to avoid unextend()
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2019-09-25
Eddie Hung
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
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2019-09-25
SergeyDegtyar
Change sync controls to async.
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2019-09-25
Clifford Wolf
Merge pull request #1402 from YosysHQ/clifford/portlist
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2019-09-25
Clifford Wolf
Improve "portlist" command
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2019-09-24
Clifford Wolf
Add "portlist" command
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2019-09-24
SergeyDegtyar
adffs test update (equiv_opt -multiclock).
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2019-09-24
Eddie Hung
Add (* techmap_autopurge *) to abc_unmap.v too
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2019-09-24
Eddie Hung
"abc_padding" attr for blackbox outputs that were padde...
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2019-09-24
Eddie Hung
Force $inout.out ports to begin with '$' to indicate...
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2019-09-24
Eddie Hung
Add techmap_autopurge to outputs in abc_map.v too
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2019-09-24
Eddie Hung
Revert "Add a xilinx_finalise pass"
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2019-09-24
Eddie Hung
Revert "Remove (* techmap_autopurge *) from abc_unmap...
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2019-09-24
Eddie Hung
Revert "Vivado does not like zero width port connections"
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2019-09-24
Eddie Hung
Vivado does not like zero width port connections
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2019-09-24
Eddie Hung
Remove (* techmap_autopurge *) from abc_unmap.v since...
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2019-09-24
Eddie Hung
Add a xilinx_finalise pass
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2019-09-23
Eddie Hung
Set [AB]CASCREG to legal values
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2019-09-23
Eddie Hung
Comment to explain separating CREG packing
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2019-09-23
Eddie Hung
Separate out CREG packing into new pattern, to avoid...
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2019-09-23
Eddie Hung
Move log_debug("\n") later
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2019-09-23
Eddie Hung
Move unextend initialisation later
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2019-09-23
Eddie Hung
Use new port() overload once more
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2019-09-23
Miodrag Milanović
Merge pull request #1399 from nakengelhardt/fix-show...
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2019-09-23
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-09-23
N. Engelhardt
add xdot dependency to Brewfile
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2019-09-23
N. Engelhardt
fix show command for macos
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2019-09-21
Clifford Wolf
Merge pull request #1392 from YosysHQ/eddie/fix1391
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2019-09-21
Eddie Hung
Hell let's add the original #1381 testcase too
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2019-09-21
Eddie Hung
Revert abc9.cc
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2019-09-21
Eddie Hung
Add testcase
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2019-09-21
Eddie Hung
Trim mismatched connection to be same (smallest) size
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2019-09-21
Eddie Hung
Fix first testcase in #1391
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2019-09-20
Eddie Hung
Grammar
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2019-09-20
Eddie Hung
Use new port/param overload in pmg
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2019-09-20
Eddie Hung
Output pattern matcher items as log_debug()
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2019-09-20
Eddie Hung
OPMODE is port not param
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2019-09-20
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-09-20
Eddie Hung
Do not run xilinx_dsp_cascadeAB for now
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2019-09-20
Eddie Hung
WIP for xiinx_dsp_cascadeAB
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2019-09-20
Eddie Hung
Run until convergence
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2019-09-20
Eddie Hung
Cleanup ice40_dsp.pmg
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2019-09-20
Eddie Hung
Cleanup xilinx_dsp
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2019-09-20
Eddie Hung
More exceptions
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2019-09-20
Eddie Hung
Fix signedness bug
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2019-09-20
Eddie Hung
Update doc
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2019-09-20
Eddie Hung
Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT
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2019-09-20
Eddie Hung
Add an overload for port/param with default value
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2019-09-20
Eddie Hung
Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine...
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2019-09-20
Eddie Hung
Revert "Move mul2dsp before wreduce"
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2019-09-20
Eddie Hung
Move mul2dsp before wreduce
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2019-09-20
Eddie Hung
Small cleanup
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2019-09-20
Clifford Wolf
Merge pull request #1386 from YosysHQ/clifford/fix1360
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2019-09-20
Clifford Wolf
Fix handling of read_verilog config in AstModule::repro...
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2019-09-20
Clifford Wolf
Update CHANGELOG
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2019-09-20
Clifford Wolf
Add "add -mod"
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2019-09-20
Clifford Wolf
Merge pull request #1384 from YosysHQ/clifford/fix1381
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2019-09-20
Eddie Hung
Disable support for SB_MAC16 reset since it is async
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