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riscv-isa-sim.git
2017-04-17
Megan Wachs
Merge remote-tracking branch 'origin/priv-1.10' into...
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2017-04-11
Andrew Waterman
Implement new FP encoding
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2017-04-08
Andrew Waterman
Implement vectored interrupt proposal
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2017-04-06
Andrew Waterman
Add --enable-misaligned option for misaligned ld/st...
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2017-04-01
Yunsup Lee
update encoding.h to get PMP updates
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2017-04-01
Andrew Waterman
Update LICENSE copyright date
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2017-03-30
Wesley W. Terpstra
fdt: move interrupt controller into its own node
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2017-03-28
Andrew Waterman
Set badaddr=0 on illegal instruction traps
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2017-03-28
Andrew Waterman
On EBREAK, set badaddr to pc
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2017-03-27
Andrew Waterman
Separate page faults from physical memory access exceptions
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2017-03-25
Andrew Waterman
Default to 2 GiB of memory
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2017-03-23
Andrew Waterman
Require little-endian host
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2017-03-22
Wesley W. Terpstra
riscv: replace rtc device with a real clint implementation
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2017-03-22
Wesley W. Terpstra
sim: declare cores as interrupt-controllers for clint
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2017-03-21
Wesley W. Terpstra
bootrom: set a0 to hartid and a1 to dtb before boot
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2017-03-21
Wesley W. Terpstra
configstring: rename variables to dts
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2017-03-21
Wesley W. Terpstra
riscv: remove dependency on num_cores
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2017-03-21
Wesley W. Terpstra
bootrom: include compiled dtb
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2017-03-21
Wesley W. Terpstra
sim: create DTS instead of config string
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2017-03-21
Wesley W. Terpstra
sim: define emulated CPU clock rate to be 1GHz
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2017-03-21
Wesley W. Terpstra
autoconf: put location of 'dtc' into config.h
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2017-03-21
Palmer Dabbelt
spec bump
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2017-03-20
Andrew Waterman
PUM -> SUM; expose MXR to S-mode
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2017-03-16
Andrew Waterman
Simplify interrupt-stack discipline
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2017-03-13
Andrew Waterman
Implement mstatus.TW, mstatus.TVM, and mstatus.TSR
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2017-03-07
Andrew Waterman
Don't overload illegal instruction trap in interactive...
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2017-02-27
Andrew Waterman
Sv57 and Sv64 are not spec'd yet
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2017-02-25
Andrew Waterman
New counter enable scheme
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2017-02-25
Tim Newsome
Update bits to latest spec.
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2017-02-23
Tim Newsome
Implement halt request.
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2017-02-22
Tim Newsome
Improve debug performance.
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2017-02-22
Tim Newsome
Don't waste time spinning in place in debug mode
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2017-02-21
Andrew Waterman
serialize simulator on wfi
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2017-02-21
Andrew Waterman
Take M-mode interrupts over S-mode interrupts
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2017-02-21
Andrew Waterman
permit MMIO loads to MSIP bit
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2017-02-19
Andrew Waterman
Make HW setting of PTE A/D bits optional (by configure...
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2017-02-18
Andrew Waterman
Spike uarch needs TLB flush after SPTBR write
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2017-02-18
Tim Newsome
Compress log output of jump-to-self loops.
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2017-02-16
Tim Newsome
Remove noisy debugs.
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2017-02-16
Tim Newsome
Set cmderr when data is accessed while busy.
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2017-02-16
Tim Newsome
Implement autoexec. DMI op 2 is just write now.
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2017-02-15
Tim Newsome
Implement resume (untested).
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2017-02-15
Andrew Waterman
sfence.vm -> sfence.vma
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2017-02-14
Tim Newsome
Implement program buffer preexec/postexec.
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2017-02-13
Tim Newsome
dbus -> dmi
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2017-02-13
Tim Newsome
Abstract register read mostly working.
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2017-02-12
Tim Newsome
Fix stack overflow and support --rbb-port=0
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2017-02-11
Tim Newsome
Entering debug mode now jumps to "dynamic rom"
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2017-02-10
Tim Newsome
Implement hartstatus field.
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2017-02-10
Tim Newsome
Remove gdbserver support.
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2017-02-09
Tim Newsome
Add writable ibuf and data registers.
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2017-02-09
Tim Newsome
Serve up a correct dmcontrol register.
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2017-02-08
Andrew Waterman
Encode VM type in sptbr, not mstatus
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2017-02-07
Tim Newsome
OpenOCD does a dmi read and gets dummy value back.
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2017-02-07
Tim Newsome
Merge pull request #83 from bacam/gdb-protocol-fixes
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2017-02-07
Tim Newsome
Remove unnecessary circular buffer code.
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2017-02-07
Tim Newsome
Refactor remote bitbang code.
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2017-02-03
Tim Newsome
OpenOCD RISC-V code now gets to scan out dtmcontrol.
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2017-02-03
Tim Newsome
OpenOCD can now scan out the hacked IDCODE.
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2017-02-03
Tim Newsome
OpenOCD connects, and sends some data that we receive.
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2017-02-03
Andrew Waterman
Fix interrupt delegation for coprocessors
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2017-02-02
Andrew Waterman
For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonica...
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2017-02-02
Andrew Waterman
Set xPIE=1 on xRET
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2017-01-08
Andrew Waterman
Only allow SIP.SSIP to be toggled if the interrupt...
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2017-01-08
Andrew Waterman
Make SIP.STIP read-only
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2017-01-06
David Craven
Comply with GNU coding standards.
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2016-12-30
Brian Campbell
Only read exception flag in gdb register read/write...
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2016-12-21
Brian Campbell
Fix gdb communication error (#82)
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2016-12-21
Brian Campbell
Remove extra gdb protocol responses on register writes
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2016-12-21
Brian Campbell
Fix gdb protocol register read of S0
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2016-12-17
Stefan O'Rear
Use correct format codes for reg_t and size_t
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2016-12-16
Tim Newsome
Fix single stepping over faulting instructions. (#80)
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2016-12-12
Tim Newsome
Reuse the ebreak constants in encoding.h.
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2016-12-01
Andy Wright
Added comments about the modified Duff's Device in...
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2016-11-14
Andrew Waterman
Fix 32-bit host portability bug
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2016-11-12
Ben Gamari
Ensure that g++ knows it is building a PCH (#75)
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2016-11-10
Andrew Waterman
AMOs should always return store faults, not load faults
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2016-10-31
Tim Newsome
Make reading/writing fpu regs work.
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2016-10-31
Tim Newsome
Minor code cleanup.
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2016-10-31
Tim Newsome
Check for exception after register write.
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2016-10-28
Tim Newsome
Check for exception after reading a register.
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2016-10-28
Tim Newsome
Fix error message.
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2016-10-25
Tim Newsome
Increase gdb receive buffer.
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2016-10-10
Andrew Waterman
Don't force load trigger timing to After
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2016-10-07
Tim Newsome
Don't die when gdb thinks XLEN is 64 but it's 32.
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2016-09-30
Tim Newsome
Return an error to gdb when memory reads fail. (#71)
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2016-09-29
Tim Newsome
Update trigger behavior. (#70)
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2016-09-13
Scott Beamer
restore clang support by fixing printf identifiers
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2016-09-10
Andrew Waterman
allow MAFDC bits in MISA to be modified
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2016-09-06
Tim Newsome
Remove generic debug tests. (#65)
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2016-09-02
Andrew Waterman
Merge pull request #62 from riscv/trigger
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2016-09-02
Tim Newsome
Merge branch 'master' into trigger
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2016-09-02
Tim Newsome
Rebuild debug ROM because CSR encoding changed.
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2016-09-02
Tim Newsome
Support triggers on TLB misses.
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2016-09-01
Tim Newsome
Theoretically support trigger timing.
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2016-08-31
Tim Newsome
Rename tdata[0-2] to tdata[1-3].
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2016-08-31
Tim Newsome
Save/restore tselect. Set dmode.
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2016-08-29
Tim Newsome
Fix indent.
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2016-08-29
Tim Newsome
Rename tdata0--tdata2 to tdata1--tdata3.
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2016-08-27
Andrew Waterman
Add (degenerate) performance counter facility
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