2019-02-21 |
Eddie Hung | simple_abc9 tests to now preserve memories |
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2019-02-21 |
Eddie Hung | read_aiger to also rename 0 index lut when wideports |
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2019-02-21 |
Eddie Hung | Remove swap file |
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2019-02-20 |
Eddie Hung | write_aiger: fix CI/CO and symbols |
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2019-02-20 |
Eddie Hung | Move tests/techmap/abc9 to simple_abc9 |
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2019-02-20 |
Eddie Hung | Add tests/simple_abc9 |
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2019-02-20 |
Eddie Hung | abc9 to cope with multiple modules |
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2019-02-20 |
Eddie Hung | abc9 to use & syntax for -fast, and name fixes |
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2019-02-20 |
Eddie Hung | read_aiger: new naming fixes |
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2019-02-20 |
Eddie Hung | read_aiger to name wires with internal name, less likel... |
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2019-02-20 |
Eddie Hung | write_xaiger to not write latches, CO/PO fixes |
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2019-02-20 |
Eddie Hung | synth to take -abc9 argument |
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2019-02-20 |
Eddie Hung | abc9 to cope with indexed wires when creating $lut... |
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2019-02-19 |
Eddie Hung | Add a quick abc9 test |
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2019-02-19 |
Eddie Hung | Same for ascii AIGERs too |
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2019-02-19 |
Eddie Hung | read_aiger to cope with non-unique POs |
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2019-02-19 |
Eddie Hung | Merge branch 'master' into xaig |
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2019-02-19 |
Eddie Hung | Merge pull request #805 from eddiehung/dff_init |
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2019-02-19 |
Eddie Hung | abc9 to replace $_NOT_ with $lut |
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2019-02-19 |
Eddie Hung | read_aiger to create sane $lut names, and rename when... |
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2019-02-19 |
Eddie Hung | Add comment |
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2019-02-19 |
Eddie Hung | Get rid of boost dep, fix the FIXMEs for Win32? |
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2019-02-17 |
Eddie Hung | Instead of INIT param on cells, use initial statement... |
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2019-02-17 |
Eddie Hung | Revert "Add INIT parameter to all ff/latch cells" |
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2019-02-17 |
Eddie Hung | Merge https://github.com/YosysHQ/yosys into dff_init |
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2019-02-17 |
Clifford Wolf | Merge pull request #811 from ucb-bar/firrtlfixes |
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2019-02-17 |
Eddie Hung | Get rid of debugging stuff in abc9 |
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2019-02-17 |
Eddie Hung | In read_xaiger, do not construct ConstEval for every LUT |
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2019-02-17 |
Eddie Hung | Cleanup |
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2019-02-17 |
Eddie Hung | read_aiger to ignore output = input of same wire; also... |
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2019-02-17 |
Eddie Hung | Cleanup |
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2019-02-17 |
Eddie Hung | write_xaiger to support non-bit cell connections, and... |
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2019-02-17 |
Eddie Hung | abc9 to write_aiger with -O option, and ignore dummy... |
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2019-02-17 |
Eddie Hung | write_aiger -O to write dummy output as __dummy_o__ |
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2019-02-16 |
Eddie Hung | abc9 to handle comb loops, cope with constant outputs... |
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2019-02-16 |
Eddie Hung | read_aiger to disable log_debug |
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2019-02-16 |
Eddie Hung | expose command to not skip 'internal' wires beginning... |
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2019-02-16 |
Eddie Hung | read_xaiger() to use f.read() not readsome() |
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2019-02-16 |
Eddie Hung | abc9 to cope with non-wideports, count cells properly |
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2019-02-16 |
Eddie Hung | Tidy up write_xaiger |
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2019-02-16 |
Eddie Hung | write_aiger() to perform CI/CO post-processing and... |
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2019-02-16 |
Eddie Hung | read_aiger() to cope with constant outputs, mixed widep... |
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2019-02-15 |
Eddie Hung | Move lookup inside if |
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2019-02-15 |
Eddie Hung | Fixes needed for DFF circuits |
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2019-02-15 |
Eddie Hung | Refactor |
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2019-02-15 |
Eddie Hung | Cope with width != 1 when re-mapping cells |
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2019-02-15 |
Jim Lawson | Removed unused variables, functions. |
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2019-02-15 |
Jim Lawson | Append (instead of over-writing) EXTRA_FLAGS |
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2019-02-15 |
Eddie Hung | abc9 to stitch results with CI/CO properly |
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2019-02-15 |
Eddie Hung | read_aiger with more asserts, and call clean |
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2019-02-15 |
Eddie Hung | write_xaiger to cope with unknown cells by transforming... |
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2019-02-15 |
Jim Lawson | Update cells supported for verilog to FIRRTL conversion. |
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2019-02-14 |
Eddie Hung | More cleanup |
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2019-02-14 |
Eddie Hung | More cleanup of write_xaiger |
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2019-02-14 |
Eddie Hung | Get rid of formal stuff from xaiger backend |
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2019-02-14 |
Eddie Hung | synth_ice40 to have new -abc9 arg |
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2019-02-14 |
Eddie Hung | Leave FIXME for clean |
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2019-02-14 |
Eddie Hung | Use module->addLut() |
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2019-02-14 |
Eddie Hung | Fix stitching |
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2019-02-14 |
Eddie Hung | Use ConstEval to compute LUT masks |
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2019-02-13 |
Eddie Hung | Merge remote-tracking branch 'origin/read_aiger' into... |
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2019-02-13 |
Eddie Hung | Merge https://github.com/YosysHQ/yosys into xaig |
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2019-02-13 |
Eddie Hung | Rip out some more stuff |
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2019-02-13 |
Clifford Wolf | Fix sign handling of real constants |
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2019-02-13 |
Eddie Hung | Rip out unused functions in abc9 |
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2019-02-12 |
Eddie Hung | Add support for read_aiger -wideports |
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2019-02-12 |
Eddie Hung | Add support for read_aiger -map |
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2019-02-12 |
Eddie Hung | Parse 'm' in xaiger |
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2019-02-12 |
Eddie Hung | WIP for ABC with aiger |
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2019-02-12 |
Eddie Hung | Missing headers for Xcode? |
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2019-02-12 |
Eddie Hung | Merge branch 'read_aiger' of github.com:eddiehung/yosys... |
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2019-02-12 |
Eddie Hung | Use module->add{Not,And}Gate() functions |
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2019-02-12 |
Clifford Wolf | Merge pull request #802 from whitequark/write_verilog_a... |
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2019-02-12 |
Clifford Wolf | Merge pull request #806 from daveshah1/fsm_opt_no_reset |
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2019-02-11 |
Eddie Hung | Add read_xaiger |
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2019-02-11 |
Eddie Hung | Add write_xaiger |
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2019-02-11 |
Eddie Hung | Do not break for constraints |
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2019-02-11 |
Eddie Hung | No increment line_count for binary ANDs |
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2019-02-11 |
Eddie Hung | Do not ignore newline after AND in binary AIG |
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2019-02-08 |
Eddie Hung | Copy backends/aiger/aiger.cc to xaiger.cc |
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2019-02-08 |
Eddie Hung | Merge remote-tracking branch 'origin/dff_init' into... |
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2019-02-08 |
Eddie Hung | Compile abc9 |
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2019-02-08 |
Eddie Hung | Refactor kernel/cost.h definition into cost.cc |
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2019-02-08 |
Eddie Hung | Copy abc.cc to abc9.cc |
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2019-02-08 |
Eddie Hung | addDff -> addDffGate as per @daveshah1 |
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2019-02-08 |
Eddie Hung | Fix tabulation |
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2019-02-08 |
Eddie Hung | -module_name arg to go before -clk_name |
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2019-02-08 |
Eddie Hung | Support and differentiate between ASCII and binary... |
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2019-02-08 |
Eddie Hung | Add missing "[options]" to read_blif help |
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2019-02-08 |
Eddie Hung | Allow module name to be determined by argument too |
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2019-02-08 |
Eddie Hung | Refactor into AigerReader class |
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2019-02-08 |
Eddie Hung | Parse binary AIG files |
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2019-02-08 |
Eddie Hung | Add binary AIGs converted from AAG |
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2019-02-08 |
Eddie Hung | Refactor to parse_aiger_header() |
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2019-02-08 |
Eddie Hung | Add comment |
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2019-02-08 |
Eddie Hung | Handle reset logic in latches |
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2019-02-08 |
Eddie Hung | Change literal vars from int to unsigned |
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2019-02-08 |
Eddie Hung | Create clk outside of latch loop |
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2019-02-08 |
Eddie Hung | Handle latch symbols too |
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2019-02-08 |
Eddie Hung | Remove return after log_error |
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next |