2019-06-21 |
Clifford Wolf | Merge pull request #1116 from YosysHQ/eddie/fix1115 |
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2019-06-21 |
Eddie Hung | Fix gcc invalidation behaviour for write_aiger |
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2019-06-20 |
Eddie Hung | Add CHANGELOG entry |
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2019-06-20 |
Eddie Hung | Extend sign extension tests |
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2019-06-20 |
Eddie Hung | Maintain "is_unsized" state of constants |
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2019-06-20 |
Eddie Hung | Revert "Fix sign extension when sign is 1'bx" |
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2019-06-20 |
Eddie Hung | Remove leftover comment |
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2019-06-20 |
Eddie Hung | Add test |
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2019-06-20 |
Eddie Hung | Fix sign extension when sign is 1'bx |
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2019-06-20 |
Clifford Wolf | Fix typo, fixes #1095 |
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2019-06-20 |
Clifford Wolf | Improve shregmap help message, fixes #1113 |
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2019-06-20 |
Clifford Wolf | Update some .gitignore files |
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2019-06-20 |
Clifford Wolf | Fix typo |
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2019-06-20 |
Clifford Wolf | Merge branch 'towoe-unpacked_arrays' |
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2019-06-20 |
Clifford Wolf | Add proper test for SV-style arrays |
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2019-06-20 |
Clifford Wolf | Merge branch 'unpacked_arrays' of https://github.com... |
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2019-06-19 |
Eddie Hung | Merge pull request #1111 from acw1251/help_summary_fixes |
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2019-06-19 |
acw1251 | Fixed small typo in ice40_unlut help summary |
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2019-06-19 |
acw1251 | Fixed the help summary line for a few commands |
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2019-06-19 |
Eddie Hung | Fix bug in #1078, add entry to CHANGELOG |
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2019-06-19 |
Clifford Wolf | Merge pull request #1109 from YosysHQ/clifford/fix1106 |
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2019-06-19 |
Clifford Wolf | Add "read_verilog -pwires" feature, closes #1106 |
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2019-06-19 |
Clifford Wolf | Merge pull request #1105 from YosysHQ/clifford/fixlogicinit |
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2019-06-19 |
Tobias Wölfel | Unpacked array declaration using size |
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2019-06-19 |
Clifford Wolf | Make tests/aiger less chatty |
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2019-06-19 |
Clifford Wolf | Add defvalue test, minor autotest fixes for .sv files |
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2019-06-19 |
Clifford Wolf | Use input default values in hierarchy pass |
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2019-06-19 |
Clifford Wolf | Add defaultvalue attribute |
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2019-06-19 |
Clifford Wolf | Fix handling of "logic" variables with initial value |
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2019-06-19 |
Clifford Wolf | Merge pull request #1100 from bwidawsk/home |
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2019-06-19 |
Clifford Wolf | Merge pull request #1104 from whitequark/case-semantics |
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2019-06-19 |
whitequark | Explain exact semantics of switch and case rules in... |
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2019-06-19 |
whitequark | In RTLIL::Module::check(), check process invariants. |
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2019-06-18 |
Ben Widawsky | Support filename rewrite in backends |
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2019-06-18 |
Ben Widawsky | Support ~ for home directory |
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2019-06-18 |
Clifford Wolf | Merge pull request #1086 from udif/pr_elab_sys_tasks2 |
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2019-06-16 |
Clifford Wolf | Add timescale and generated-by header to yosys-smtbmc... |
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2019-06-13 |
Serge Bazanski | Merge pull request #829 from abdelrahmanhosny/master |
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2019-06-10 |
Udi Finkelstein | Fixed brojen $error()/$info/$warning() on non-generate... |
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2019-06-10 |
Eddie Hung | Add some more comments |
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2019-06-10 |
David Shah | Merge pull request #1082 from corecode/u4k |
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2019-06-10 |
Simon Schubert | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR... |
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2019-06-08 |
Clifford Wolf | Merge pull request #1078 from YosysHQ/eddie/muxcover_costs |
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2019-06-07 |
Eddie Hung | Fix spacing from spaces to tabs |
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2019-06-07 |
Clifford Wolf | Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger |
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2019-06-07 |
Eddie Hung | Add read_aiger to CHANGELOG |
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2019-06-07 |
Eddie Hung | Fix spacing (entire file is wrong anyway, will fix... |
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2019-06-07 |
Eddie Hung | Remove unnecessary std::getline() for ASCII |
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2019-06-07 |
Eddie Hung | Test *.aag too, by using *.aig as reference |
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2019-06-07 |
Eddie Hung | Fix read_aiger -- create zero driver, fix init width... |
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2019-06-07 |
Eddie Hung | Use ABC to convert from AIGER to Verilog |
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2019-06-07 |
Eddie Hung | Use ABC to convert AIGER to Verilog, then sat against... |
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2019-06-07 |
Eddie Hung | Add symbols to AIGER test inputs for ABC |
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2019-06-07 |
Eddie Hung | Allow muxcover costs to be changed |
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2019-06-07 |
Clifford Wolf | Merge pull request #1077 from YosysHQ/clifford/pr983 |
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2019-06-07 |
Clifford Wolf | Rename implicit_ports.sv test to implicit_ports.v |
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2019-06-07 |
Clifford Wolf | Fixes and cleanups in AST_TECALL handling |
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2019-06-07 |
Clifford Wolf | Merge branch 'pr_elab_sys_tasks' of https://github... |
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2019-06-07 |
Clifford Wolf | Merge branch 'tux3-implicit_named_connection' |
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2019-06-07 |
Clifford Wolf | Merge pull request #1076 from thasti/centos7-build-fix |
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2019-06-07 |
Clifford Wolf | Cleanup tux3-implicit_named_connection |
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2019-06-07 |
Clifford Wolf | Merge branch 'implicit_named_connection' of https:... |
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2019-06-07 |
Stefan Biereigel | remove boost/log/exceptions.hpp from wrapper generator |
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2019-06-06 |
tux3 | SystemVerilog support for implicit named port connections |
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2019-06-06 |
Clifford Wolf | Merge pull request #1060 from antmicro/parsing_attr_on_... |
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2019-06-06 |
David Shah | Merge pull request #1073 from whitequark/ecp5-diamond-iob |
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2019-06-06 |
whitequark | ECP5: implement all Diamond I/O buffer primitives. |
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2019-06-06 |
Clifford Wolf | Merge pull request #1071 from YosysHQ/eddie/fix_1070 |
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2019-06-06 |
Clifford Wolf | Merge pull request #1072 from YosysHQ/eddie/fix_1069 |
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2019-06-05 |
Eddie Hung | Missing doc for -tech xilinx in shregmap |
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2019-06-05 |
Eddie Hung | Error out if no top module given before 'sim' |
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2019-06-05 |
Eddie Hung | Fix typo in opt_rmdff |
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2019-06-05 |
Eddie Hung | Merge pull request #1067 from YosysHQ/clifford/fix1065 |
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2019-06-05 |
Maciej Kurc | Fixed memory leak. |
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2019-06-05 |
Clifford Wolf | Merge pull request #1066 from YosysHQ/clifford/fix1056 |
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2019-06-05 |
Clifford Wolf | Major rewrite of wire selection in setundef -init |
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2019-06-05 |
Clifford Wolf | Indent fix |
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2019-06-05 |
Clifford Wolf | Merge pull request #999 from jakobwenzel/setundefInitFix |
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2019-06-05 |
Clifford Wolf | Fix typo in fmcombine log message, fixes #1063 |
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2019-06-05 |
Clifford Wolf | Suppress driver-driver conflict warning for unknown... |
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2019-06-05 |
Clifford Wolf | Remove yosys_banner() from python wrapper init, fixes... |
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2019-06-04 |
Clifford Wolf | Merge pull request #1062 from tux3/patch-1 |
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2019-06-04 |
Tux3 | README.md: Missing formatting for <tag> |
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2019-06-04 |
Maciej Kurc | Moved tests that fail with Icarus Verilog to /tests... |
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2019-06-04 |
Eddie Hung | Merge pull request #1061 from YosysHQ/eddie/techmap_and... |
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2019-06-04 |
Eddie Hung | Remove extra newline |
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2019-06-04 |
Eddie Hung | Execute techmap and arith_map simultaneously |
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2019-06-03 |
Maciej Kurc | Added tests for attributes |
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2019-06-02 |
Clifford Wolf | Only support Symbiotic EDA flavored Verific |
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2019-05-31 |
Maciej Kurc | Added support for parsing attributes on port connections. |
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2019-05-31 |
Clifford Wolf | Fix "tee" handling of log_streams |
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2019-05-30 |
Clifford Wolf | Enable Verific flag veri_elaborate_top_level_modules_ha... |
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2019-05-30 |
Clifford Wolf | Merge pull request #1057 from mmicko/fix_478 |
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2019-05-29 |
Miodrag Milanovic | Aded one more load of .conf to support change of prefix |
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2019-05-28 |
Clifford Wolf | Merge pull request #1049 from YosysHQ/clifford/fix1047 |
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2019-05-28 |
Clifford Wolf | Merge pull request #1050 from YosysHQ/clifford/wandwor |
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2019-05-28 |
Clifford Wolf | Do not use shiftmul peepopt pattern when mul result... |
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2019-05-28 |
Clifford Wolf | Merge pull request #1048 from mmicko/fix_enable_pyosys |
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2019-05-28 |
Clifford Wolf | Refactor hierarchy wand/wor handling |
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2019-05-28 |
Clifford Wolf | Add actual wandwor test that is part of "make test" |
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