gem5.git
2012-03-01 Dam SunwooARM: move kernel func event to correct location.
2012-03-01 Giacomo GabrielliARM: fix bits-to-fp conversion function declarations.
2012-03-01 Nilay Vaishx86: Fix x86 TLB and Walker
2012-03-01 Nilay Vaishx86: Fix switching of CPUs
2012-03-01 Nilay VaishConfig: make option ruby available always
2012-02-29 Andreas HanssonMEM: Make all the port proxy members const
2012-02-29 Andreas HanssonSWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1
2012-02-29 Steve ReinhardtEIO: update stats (mostly order change, some renames)
2012-02-26 Gabe BlackMake the IO bridge accept address headed to all the...
2012-02-26 Gabe BlackX86: Use the M5PanicFault fault in execute methods...
2012-02-24 Andreas HanssonMEM: Simplify cache ports preparing for master/slave...
2012-02-24 Andreas HanssonMEM: Prepare mport for master/slave split
2012-02-24 Andreas HanssonRuby: Simplify tester ports by not using SimpleTimingPort
2012-02-24 Andreas HanssonMEM: Move all read/write blob functions from Port to...
2012-02-24 Andreas HanssonMEM: Make port proxies use references rather than pointers
2012-02-24 Andreas HanssonMEM: Move port creation to the memory object(s) constru...
2012-02-24 Andreas HanssonCPU: Round-two unifying instr/data CPU ports across...
2012-02-24 Andreas HanssonMEM: Fatal when no port can be found for an address
2012-02-20 Steve ReinhardtSimObject: make get_config_as_dict() tolerate undefined...
2012-02-14 Andreas HanssonMEM: Fix residual bus ports and make them master/slave
2012-02-14 Andreas HanssonScript: Fix the scripts that use the num_cpus cache...
2012-02-14 Andreas HanssonMEM: Fix master/slave ports in Ruby and non-regression...
2012-02-13 Ali Saidibp: fix up stats for changes to branch predictor
2012-02-13 Mrinmoy GhoshBPred: Fix RAS to handle predicated call/return instruc...
2012-02-13 Mrinmoy GhoshBP: Fix several Branch Predictor issues.
2012-02-13 Andreas HanssonMEM: Explicit ports and Python binding on CopyEngine
2012-02-13 Andreas HanssonMEM: Pass the ports from Python to C++ using the Swig...
2012-02-13 Andreas HanssonMEM: Introduce the master/slave port roles in the Pytho...
2012-02-13 Ali Saiditests: fix diff-out script for op/inst stat changes.
2012-02-13 Gabe BlackX86: open flags: Another patch from Vince Weaver
2012-02-12 Ali Saidiconfigs: fix minor config bugs posted on the mailing...
2012-02-12 Ali Saidistats: update stats for insts/ops and master id changes
2012-02-12 Anthony Gutierrezcpu: add separate stats for insts/ops both globally...
2012-02-12 Dam Sunwoomem: fix cache stats to use request ids correctly
2012-02-12 Ali Saidimem: Add a master ID to each request object.
2012-02-12 Mrinmoy Ghoshprefetcher: Make prefetcher a sim object instead of...
2012-02-12 Nilay VaishRegressions: Update stats due to change in MESI protocol
2012-02-11 Gabe BlackSPARC: Make PSTATE and HPSTATE a BitUnion.
2012-02-10 Nilay VaishRuby: Remove isTagPresent() calls from Sequencer.cc
2012-02-10 Nilay VaishMESI: Add queues for stalled requests
2012-02-10 Nilay Vaishsim/system: initialize the pagePtr variable
2012-02-10 Nilay VaishRegressions: Update stats due to O3 CPU changes
2012-02-10 Nilay VaishO3 CPU: Improve handling of delayed commit flag
2012-02-10 Nilay VaishO3 CPU: Strengthen condition for handling interrupts
2012-02-10 Nilay VaishO3 CPU: Provide the squashing instruction
2012-02-10 Nilay VaishO3 Fetch: Check if PC is pointing to Microcode ROM
2012-02-10 Gabe BlackSE/FS: Record the system pointer all the time for the...
2012-02-09 Andreas HanssonMEM: Remove onRetryList from BusPort and rely on retryList
2012-02-07 Gabe BlackChecker: Access workload element 0 only if there is...
2012-02-07 Gabe BlackFaults: Turn off arch/faults.hh
2012-02-07 Gabe Blackm5=>gem5: Make the regression script build gem5.* inste...
2012-02-05 Gabe BlackX86: Rename the bridge which allows commnication back...
2012-02-05 Gabe BlackRegressions: Fix the regress script when "all" is used.
2012-02-03 Gabe BlackSystem: Forgot to qrefresh with my last change.
2012-02-03 Gabe BlackSystem: Fix the check which detects running out of...
2012-02-02 Andreas HanssonRegression: Update the regress script after SE/FS merge
2012-02-01 Ali Saidiconfigs: More fixes for the memory system updates
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Koan-Sin Tanclang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 Andreas HanssonMEM: Remove the otherPort from the cache ports
2012-01-31 Andreas HanssonThread: Use inherited baseCpu rather than cpu in Simple...
2012-01-31 Dam Sunwooutil: implements "writefile" gem5 op to export file...
2012-01-31 Geoffrey BlakeCheckerCPU: Re-factor CheckerCPU to be compatible with...
2012-01-31 Gabe BlackMerge with main repository.
2012-01-30 Andreas HanssonRuby: Connect system port in Ruby network test
2012-01-30 Andreas HanssonMEM: Make the RubyPort physMemPort a PioPort instead...
2012-01-30 Andreas HanssonMEM: Clean-up of Functional/Virtual/TranslatingPort...
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-29 Gabe BlackImplement Ali's review feedback.
2012-01-29 Nilay VaishConfig: Enable O3 CPU and Ruby in FS mode
2012-01-29 Nilay VaishX86 Regressions: Update stats due to introduction of TSO
2012-01-29 Nilay VaishO3 CPU LSQ: Implement TSO
2012-01-28 Gabe BlackSE/FS: Get rid of the FULL_SYSTEM config option.
2012-01-28 Gabe BlackSE/FS: Pull FULL_SYSTEM out of the build_opts files
2012-01-28 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in the configs directory
2012-01-28 Gabe BlackSE/FS: Make both SE and FS tests available all the...
2012-01-28 Gabe BlackSE/FS: Make SE vs. FS mode a runtime parameter.
2012-01-28 Gabe BlackMIPS: Fix a compiler warning from the eret instruction.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-27 Andreas Hanssonns_gige: Fix a missing curly brace in if-statement
2012-01-26 Ronald Dreslinskiconfigs: actually add ARMv7a-like cpu/cache file
2012-01-26 Ronald Dreslinskiconfigs: A more realistic configuration of an ARM-like...
2012-01-25 Andreas HanssonMEM: Fix fs.py by specifying the range size rather...
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-12 Mitchell HayengaFix memory corruption issue with CopyStringOut()
2012-01-25 Ali Saidistats: Update stats for final tick and memory bandwidth...
2012-01-25 Ali Saidisim: display final value of curTick in stats
2012-01-25 Ali SaidiMem: Add simple bandwidth stats to PhysicalMemory
2012-01-23 Nilay VaishConfig: Enable using O3 CPU and Ruby in SE mode
2012-01-23 Nilay VaishO3, Ruby: Forward invalidations from Ruby to O3 CPU
2012-01-23 Nilay VaishMemCmd: Add a command for invalidation requests to LSQ
2012-01-17 Andreas HanssonMEM: Make the bus default port yet another port
2012-01-17 Andreas HanssonMEM: Removing the default port peer from Python ports
2012-01-17 Andreas HanssonMEM: Make the bus bridge unidirectional and fixed addre...
2012-01-17 William WangMEM: Remove the functional ports from the memory system
2012-01-17 Andreas HanssonMEM: Separate queries for snooping and address ranges
2012-01-17 Andreas HanssonMEM: Remove Port removeConn and MemObject deletePortRefs
2012-01-17 Andreas HanssonMEM: Remove the notion of the default port
2012-01-17 Andreas HanssonMEM: Simplify ports by removing EventManager
2012-01-17 Andreas HanssonCPU: Moving towards a more general port across CPU...
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