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yosys.git
2019-05-04
Clifford Wolf
Improve write_verilog specify support
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2019-05-04
Clifford Wolf
Update README
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2019-05-03
Eddie Hung
More testing
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2019-05-03
Eddie Hung
Fix spacing
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2019-05-03
Eddie Hung
Add quick-and-dirty specify tests
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2019-05-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into cliff...
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2019-05-03
Eddie Hung
Rename cells_map.v to prevent clash with ff_map.v
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2019-05-03
Eddie Hung
iverilog with simcells.v as well
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2019-05-03
Clifford Wolf
Merge pull request #969 from YosysHQ/clifford/pmgenstuff
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2019-05-03
Clifford Wolf
Merge pull request #984 from YosysHQ/eddie/fix_982
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2019-05-03
Eddie Hung
Revert "synth_xilinx to call dffinit with -noreinit"
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2019-05-03
Eddie Hung
If init is 1'bx, do not add to dict as per @cliffordwolf
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2019-05-03
Eddie Hung
Revert "dffinit -noreinit to silently continue when...
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2019-05-03
Clifford Wolf
Merge pull request #976 from YosysHQ/clifford/fix974
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2019-05-03
Clifford Wolf
Merge pull request #985 from YosysHQ/clifford/fix981
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2019-05-03
Clifford Wolf
Fix typo in tests/svinterfaces/runone.sh
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2019-05-03
Clifford Wolf
Merge pull request #979 from jakobwenzel/svinterfacesTe...
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2019-05-03
Clifford Wolf
Improve opt_expr and opt_clean handling of (partially...
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2019-05-03
Clifford Wolf
Update pmgen documentation
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2019-05-03
Clifford Wolf
Fix typo
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2019-05-03
Eddie Hung
synth_xilinx to call dffinit with -noreinit
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2019-05-03
Eddie Hung
dffinit -noreinit to silently continue when init value...
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2019-05-02
Jakob Wenzel
fail svinterfaces testcases on yosys error exit
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2019-05-02
Clifford Wolf
Merge pull request #963 from YosysHQ/eddie/synth_xilinx...
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2019-05-02
Eddie Hung
Merge pull request #978 from ucb-bar/fmtfirrtl
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2019-05-02
Eddie Hung
Back to passing all xc7srl tests!
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2019-05-02
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-05-01
Eddie Hung
Merge branch 'master' of github.com:YosysHQ/yosys
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2019-05-01
Jim Lawson
Re-indent firrtl.cc:struct memory - no functional change.
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2019-05-01
Clifford Wolf
Merge branch 'clifford/fix883'
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2019-05-01
Clifford Wolf
Add missing enable_undef to "sat -tempinduct-def",...
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2019-05-01
Clifford Wolf
Merge pull request #977 from ucb-bar/fixfirrtlmem
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2019-05-01
Jim Lawson
Fix #938 - Crash occurs in case when use write_firrtl...
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2019-05-01
Clifford Wolf
Fix floating point exception in qwp, fixes #923
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2019-05-01
Clifford Wolf
Add splitcmplxassign test case and silence splitcmplxas...
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2019-05-01
Clifford Wolf
Fix width detection of memory access with bit slice...
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2019-04-30
Clifford Wolf
Fix segfault in wreduce
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2019-04-30
Clifford Wolf
Disabled "final loop assignment" feature
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2019-04-30
Clifford Wolf
Merge pull request #972 from YosysHQ/clifford/fix968
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2019-04-30
Clifford Wolf
Merge pull request #966 from YosysHQ/clifford/fix956
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2019-04-30
Clifford Wolf
Merge pull request #962 from YosysHQ/eddie/refactor_syn...
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2019-04-30
Clifford Wolf
Merge branch 'master' into eddie/refactor_synth_xilinx
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2019-04-30
Clifford Wolf
Merge pull request #973 from christian-krieg/feature...
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2019-04-30
Clifford Wolf
Include filename in "Executing Verilog-2005 frontend...
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2019-04-30
Clifford Wolf
Fix performance bug in RTLIL::SigSpec::operator==(...
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2019-04-30
Clifford Wolf
Add final loop variable assignment when unrolling for...
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2019-04-30
Clifford Wolf
Add handling of init attributes in "opt_expr -undriven"
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2019-04-30
Benedikt Tutzer
Merge branch 'master' of https://github.com/YosysHQ...
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2019-04-30
Benedikt Tutzer
Cleaned up root directory
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2019-04-30
Clifford Wolf
Add peepopt_muldiv, fixes #930
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2019-04-30
Clifford Wolf
pmgen progress
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2019-04-30
Clifford Wolf
Run "peepopt" in generic "synth" pass and "synth_ice40"
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2019-04-30
Clifford Wolf
Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmu...
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2019-04-30
Clifford Wolf
Progress in shiftmul peepopt pattern
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2019-04-29
Clifford Wolf
Merge pull request #960 from YosysHQ/eddie/equiv_opt_undef
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2019-04-29
Clifford Wolf
Merge pull request #967 from olegendo/depfile_esc_spaces
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2019-04-29
Clifford Wolf
Add "peepopt" skeleton
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2019-04-29
Clifford Wolf
Add pmgen support for multiple patterns in one matcher
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2019-04-29
Oleg Endo
fix codestyle formatting
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2019-04-29
Clifford Wolf
Support multiple pmg files (right now just concatenated...
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2019-04-29
Oleg Endo
escape spaces with backslash when writing dep file
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2019-04-29
Clifford Wolf
Drive dangling wires with init attr with their init...
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2019-04-28
Eddie Hung
Copy with 1'bx padding in $shiftx
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2019-04-28
Eddie Hung
WIP
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2019-04-28
Eddie Hung
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
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2019-04-26
Eddie Hung
Revert synth_xilinx 'fine' label more to how it used...
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2019-04-26
Eddie Hung
Where did this check come from!?!
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2019-04-26
Eddie Hung
Refactor synth_xilinx to auto-generate doc
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2019-04-26
Eddie Hung
Cleanup ice40
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2019-04-26
Eddie Hung
Add -undef option to equiv_opt, passed to equiv_induct
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2019-04-25
Eddie Hung
Misspelling
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2019-04-23
Clifford Wolf
Add specify support to README
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2019-04-23
Clifford Wolf
Improve $specrule interface
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2019-04-23
Clifford Wolf
Improve $specrule interface
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2019-04-23
Clifford Wolf
Add $specrule cells for $setup/$hold/$skew specify...
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2019-04-23
Clifford Wolf
Preserve $specify[23] cells
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2019-04-23
Clifford Wolf
Allow $specify[23] cells in blackbox modules
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2019-04-23
Clifford Wolf
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better...
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2019-04-23
Clifford Wolf
Add $specify2/$specify3 support to write_verilog
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2019-04-23
Clifford Wolf
Add support for $assert/$assume/$cover to write_verilog
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2019-04-23
Clifford Wolf
Add CellTypes support for $specify2 and $specify3
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2019-04-23
Clifford Wolf
Add InternalCellChecker support for $specify2 and ...
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2019-04-23
Clifford Wolf
Checking and fixing specify cells in genRTLIL
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2019-04-23
Clifford Wolf
Un-break default specify parser
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2019-04-23
Clifford Wolf
Add specify parser
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2019-04-23
Clifford Wolf
Add $specify2 and $specify3 cells to simlib
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2019-04-23
Clifford Wolf
Merge pull request #957 from YosysHQ/oai4fix
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2019-04-23
David Shah
Fixes for OAI4 cell implementation
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2019-04-23
Eddie Hung
Format some names using inline code
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2019-04-23
Eddie Hung
Fix spelling
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2019-04-23
Clifford Wolf
Remove some left-over log_dump()
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2019-04-22
Eddie Hung
Merge pull request #914 from YosysHQ/xc7srl
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2019-04-22
Eddie Hung
Update help message
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2019-04-22
Clifford Wolf
Merge pull request #952 from YosysHQ/clifford/fix370
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2019-04-22
Clifford Wolf
Merge pull request #951 from YosysHQ/clifford/logdebug
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2019-04-22
Clifford Wolf
Merge pull request #949 from YosysHQ/clifford/pmux2shim...
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2019-04-22
Clifford Wolf
Merge pull request #953 from YosysHQ/clifford/fix948
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2019-04-22
Eddie Hung
Move 'shregmap -tech xilinx' into map_cells
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2019-04-22
Clifford Wolf
Add support for zero-width signals to Verilog back...
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2019-04-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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