yosys.git
2019-04-19 Clifford WolfAdd tests/aiger/.gitignore
2019-04-19 Eddie HungSpelling fixes
2019-04-19 Eddie HungFix SB_DFF comb model
2019-04-19 Eddie HungRevert "write_json to not write contents (cells/wires...
2019-04-19 Eddie HungMissing close bracket
2019-04-19 Eddie HungAnnotate SB_DFF* with abc_flop and abc_box_id
2019-04-19 Eddie HungAdd SB_DFF* to boxes
2019-04-19 Eddie HungAdd flop support for write_xaiger
2019-04-19 Eddie Hungread_aiger to parse 'r' extension
2019-04-19 Eddie HungSpelling
2019-04-18 Clifford WolfUpdate to ABC 3709744
2019-04-18 Eddie HungMerge pull request #917 from YosysHQ/eddie/fix_retime
2019-04-18 Eddie HungUse new -wb flag for ABC flow
2019-04-18 Eddie Hungwrite_json to not write contents (cells/wires) of white...
2019-04-18 Eddie HungIgnore 'whitebox' attr in flatten with "-wb" option
2019-04-18 Eddie Hungwrite_json to not write contents (cells/wires) of white...
2019-04-18 Eddie HungIgnore 'whitebox' attr in flatten with "-wb" option
2019-04-18 Eddie HungAlso update Makefile.inc
2019-04-18 Eddie HungFix abc's remap_name to not ignore [^0-9] when extracti...
2019-04-18 Eddie HungMake SB_LUT4 a blackbox
2019-04-18 Eddie HungFix rename
2019-04-18 Eddie HungRename to abc_*.{box,lut}
2019-04-18 Eddie HungMerge remote-tracking branch 'origin/clifford/whitebox...
2019-04-18 Eddie HungABC to call retime all the time
2019-04-18 Clifford WolfAdd "whitebox" attribute, add "read_verilog -wb"
2019-04-18 Eddie HungRevert "synth_* with -retime option now calls abc with...
2019-04-18 Eddie HungMerge branch 'master' into eddie/fix_retime
2019-04-18 Clifford WolfImprove proc full_case detection and handling, fixes...
2019-04-17 Eddie HungSkip if abc_box_id earlier
2019-04-17 Eddie HungRemove use of abc_box_id in stat
2019-04-17 Eddie HungFix $anyseq warning and cleanup
2019-04-17 Eddie HungUpdate Makefile.inc too
2019-04-17 Eddie HungReduce to three devices: hx, lp, u
2019-04-17 Eddie HungDo not print slack histogram
2019-04-17 Eddie HungAdd up5k timings
2019-04-17 Eddie HungFix grammar
2019-04-17 Eddie HungUpdate error message
2019-04-17 Eddie HungAdd "-device" argument to synth_ice40
2019-04-17 Eddie HungMissing abc_flop_q attribute on SPRAM
2019-04-17 Eddie HungCope with inout ports
2019-04-17 Eddie HungMap to SB_LUT4 from fastest input first
2019-04-17 Eddie HungWorking ABC9 script
2019-04-17 Eddie HungStop topological sort at abc_flop_q
2019-04-17 Eddie HungMark seq output ports with "abc_flop_q" attr
2019-04-17 Eddie HungAlso update Makefile.inc
2019-04-17 Eddie Hungsynth_ice40 to use renamed files
2019-04-17 Eddie HungRename to abc.*
2019-04-17 Eddie HungRevert "Try using an ICE40_CARRY_LUT primitive to avoid...
2019-04-17 Eddie HungTry using an ICE40_CARRY_LUT primitive to avoid ABC...
2019-04-17 Eddie HungRemove init* from xaiger, also topo-sort cells for...
2019-04-17 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-17 Eddie HungIgnore a/i/o/h XAIGER extensions
2019-04-17 Eddie HungFix spacing
2019-04-17 Clifford WolfUpdate to ABC d1b6413
2019-04-17 Eddie HungOptimise
2019-04-17 Eddie HungAdd SB_LUT4 to box library
2019-04-16 Eddie HungAdd ice40 box files
2019-04-16 Eddie Hungabc9 to output some more info
2019-04-16 Eddie HungCIs before PIs; also sort each cell's connections befor...
2019-04-16 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-16 Eddie HungPort from xc7mux branch
2019-04-16 Eddie HungAdd MUXCY and XORCY to cells_box.v
2019-04-16 Eddie HungFix wire numbering
2019-04-16 Eddie HungDo not put constants into output_bits
2019-04-16 Eddie HungRemove write_verilog call
2019-04-16 Eddie HungFix spacing
2019-04-16 Eddie HungMerge branch 'xaig' into xc7mux
2019-04-16 Eddie HungRe-enable partsel.v test
2019-04-16 Eddie Hungabc9 to call "setundef -zero" behaving as for abc
2019-04-16 Eddie HungNULL check before use
2019-04-16 Eddie HungWIP for box support
2019-04-16 Eddie HungABC to read_box before reading netlist
2019-04-16 Eddie HungMake cells.box whiteboxes not blackboxes
2019-04-16 Eddie Hungread_verilog cells_box.v before techmap
2019-04-16 Eddie HungMerge pull request #939 from YosysHQ/revert895
2019-04-16 Eddie Hungsynth_xilinx: before abc read +/xilinx/cells_box.v
2019-04-16 Eddie HungAdd +/xilinx/cells_box.v containing models for ABC...
2019-04-16 Eddie HungFor 'stat' do not count modules with abc_box_id
2019-04-16 Eddie HungDo not call abc on modules with abc_box_id attr
2019-04-16 Eddie HungRevert "Add abc_box_id attribute to MUXF7/F8 cells"
2019-04-16 Eddie HungRevert #895
2019-04-16 Eddie HungUse abc_box_id
2019-04-16 Eddie HungCheck abc_box_id attr
2019-04-16 Eddie HungAdd abc_box_id attribute to MUXF7/F8 cells
2019-04-16 Eddie HungMerge branch 'xaig' into xc7mux
2019-04-16 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-16 Eddie HungMerge pull request #937 from YosysHQ/revert-932-eddie...
2019-04-16 Eddie HungRevert "Recognise default entry in case even if all...
2019-04-15 Eddie HungMerge pull request #936 from YosysHQ/README-fix-quotes
2019-04-15 whitequarkREADME: fix some incorrect quoting.
2019-04-13 DiegoGoWin enablement: DRAM, initial BRAM, DRAM init, DRAM...
2019-04-13 Eddie HungForgot backslashes
2019-04-13 Eddie HungHandle __dummy_o__ and __const[01]__ in read_aiger...
2019-04-13 Eddie Hungabc to ignore __dummy_o__ and __const[01]__ when re...
2019-04-13 Eddie HungOutput __const0__ and __const1__ CIs
2019-04-13 Eddie HungMerge branch 'xaig' of github.com:YosysHQ/yosys into...
2019-04-13 Eddie HungFix inout handling for -map option
2019-04-12 Eddie HungMerge branch 'xaig' of github.com:YosysHQ/yosys into...
2019-04-12 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-04-12 Eddie HungUse -map instead of -symbols for aiger
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