microwatt.git
2022-03-06 Raptor Engineering... Migrate LPC slave away from ECP5 block RAMs to Pinyon...
2022-03-06 Raptor Engineering... Add Pinyon dual port RAM interface
2022-03-02 Raptor Engineering... Fix typo
2022-03-02 Raptor Engineering... Fix incorrect Aquila core license
2022-03-01 Raptor Engineering... Documentation cleanup
2022-03-01 Raptor Engineering... Fix typo
2022-03-01 Raptor Engineering... Update documentation
2022-03-01 Raptor Engineering... Formally release this version of Aquila under the GNU...
2022-03-01 Raptor Engineering... [WIP] Add initial version of Aquila LPC slave core
2022-03-01 Raptor Engineering... Add missing mapping between HAS and USE for Liteeth...
2022-02-23 Raptor Engineering... Formally release this version of Tercel under the GNU...
2022-02-23 Raptor Engineering... Fix typo
2022-02-23 Raptor Engineering... Make Tercel register map a bit easier to read
2022-02-23 Raptor Engineering... Update Tercel README with actual core state on reset
2022-02-23 Raptor Engineering... Add Tercel support to Arty
2022-02-23 Raptor Engineering... Add initial Tercel support for Arctic Tern
2022-02-22 Raptor Engineering... Add initial Arctic Tern support
2022-02-22 Raptor Engineering... Extend LiteDRAM VHDL wrapper to allow more than one...
2022-02-22 Joel Stanleyyosys: Use read_verilog
2021-03-25 Anton BlanchardMerge pull request #286 from antonblanchard/Makefile...
2021-03-25 Anton BlanchardRemove unused GHDL_TARGET_GENERICS
2021-03-25 Anton BlanchardMove verilator --trace flag into VERILATOR_FLAGS
2021-03-24 Anton BlanchardMerge pull request #285 from antonblanchard/Makefile...
2021-03-24 Anton BlanchardMerge pull request #281 from antonblanchard/cache-tlb...
2021-03-24 Anton BlanchardRemove -frelaxed
2021-03-24 Anton BlanchardUse VERILATOR_FLAGS/VERILATOR_CFLAGS on all verilator...
2021-03-24 Anton BlanchardRemove core_files from soc_files and fpga_files
2021-03-23 Anton BlanchardMerge pull request #284 from antonblanchard/boot-clocks
2021-03-15 Anton BlanchardAllow SPI BOOT_CLOCKS to be overridden by top level
2021-03-15 Anton BlanchardPass icache/dcache/tlb parameters down from soc
2021-02-08 Michael NeulingMerge pull request #274 from mikey/read-sprs
2021-02-08 Anton BlanchardAdd a test to read from all SPRs
2021-02-08 Michael NeulingFix DAR/DSISR reading before they are written
2021-02-08 Michael NeulingMerge pull request #269 from paulusmack/pipeline
2021-02-08 Michael NeulingMerge pull request #268 from paulusmack/btc
2021-02-08 Michael NeulingMerge pull request #273 from antonblanchard/wishbone...
2021-02-08 Michael NeulingMerge pull request #267 from paulusmack/master
2021-02-08 Anton BlanchardAdd some wishbone checking
2021-01-19 Paul Mackerrascore: Allow multiple loadstore instructions to be in...
2021-01-19 Paul Mackerrasloadstore: Convert to 3-stage pipeline
2021-01-19 Paul Mackerrasdcache: Fix bugs in pipelined operation
2021-01-19 Paul Mackerrascore: Send FPU interrupts to writeback rather than...
2021-01-18 Paul Mackerrascore: Send loadstore1 interrupts to writeback rather...
2021-01-18 Paul Mackerrascore: Move redirect and interrupt delivery logic to...
2021-01-18 Paul Mackerrasexecute1: Move CR result to data path process
2021-01-18 Paul Mackerrasexecute1: Move data-path logic out to a separate process
2021-01-18 Paul Mackerrascore: Track CR hazards and bypasses using tags
2021-01-18 Paul Mackerrascore: Restore bypass path from execute1
2021-01-18 Paul Mackerrascore: Track GPR hazards using tags that propagate throu...
2021-01-18 Paul Mackerrascore: Crack branches that update both CTR and LR
2021-01-18 Paul Mackerrascore: Crack update-form loads into two internal ops
2021-01-18 Paul Mackerrasfetch1: Implement a simple branch target cache
2021-01-15 Paul Mackerrasexecute1: Improve timing on comparisons
2021-01-15 Paul Mackerrascore: Reorganize execute1
2021-01-15 Paul Mackerrasdecode1: Implement tlbsync as a no-op
2021-01-15 Paul Mackerrascore: Make result multiplexing explicit
2021-01-15 Paul Mackerrasdecode1: Implement obsolete dst, dstst, dss instruction...
2021-01-15 Paul Mackerrasexecute1: Move branch adder after register
2021-01-15 Paul Mackerrasdecode: Add a facility field to the instruction decode...
2021-01-15 Paul Mackerrasdecode1: Take an extra cycle for predicted branch redirects
2021-01-15 Paul Mackerrastests: Add tests for lq/stq and lqarx/stqcx.
2021-01-15 Paul Mackerrasloadstore1/dcache: Send store data one cycle later
2021-01-15 Paul Mackerrascore: Implement quadword loads and stores
2021-01-15 Paul Mackerrasloadstore1: Improve timing of data path from cache...
2021-01-15 Paul Mackerrasdcache: Add more commentary, no code change
2021-01-15 Paul Mackerrasloadstore1: Decide on load formatting controls a cycle...
2021-01-15 Paul Mackerrasdecode1: Fix decoding of recommended NOP instruction
2021-01-15 Paul Mackerrascore_debug: Stop logging 256 cycles after trigger
2021-01-15 Paul Mackerrascore_debug: Add an address trigger to stop logging...
2021-01-15 Paul MackerrasFPU: Don't use mask generator for rounding
2021-01-15 Paul MackerrasFPU: Relax timing around multiplier output
2021-01-15 Paul Mackerrasmw_debug: Display terminated status when stopping
2021-01-15 Paul Mackerrasmw_debug: Extend to handle FPRs
2021-01-15 Paul MackerrasArty A7: Document pin connections for on-board headers
2021-01-15 Paul Mackerrasexecute1: Update comments about XER forwarding
2021-01-07 Paul MackerrasMerge pull request #263 from antonblanchard/reset-pid
2021-01-07 Paul MackerrasMerge pull request #262 from antonblanchard/reset-tb...
2021-01-07 Paul MackerrasMerge pull request #259 from antonblanchard/dmi-reset
2021-01-05 Anton BlanchardMerge pull request #265 from antonblanchard/another...
2021-01-05 Anton BlanchardMerge pull request #264 from antonblanchard/reset-spi...
2021-01-03 Anton BlanchardInitialize PID register
2021-01-03 Anton BlanchardFix another reset issue in spi_rxtx
2021-01-03 Anton BlanchardReset cmd_ready_o in spi_txrx
2021-01-03 Anton BlanchardReset TB and DECR
2020-12-21 Anton BlanchardMerge pull request #261 from antonblanchard/wishbone_layout
2020-12-21 Anton BlanchardMerge pull request #260 from paulusmack/misc
2020-12-20 Anton BlanchardMake wishbone_master_out and wb_io_master_out match
2020-12-19 Paul Mackerrasfetch1: Fix debug stop
2020-12-17 Paul Mackerrassoc: Drive uart1_irq to 0 when we don't have UART1
2020-12-15 Anton BlanchardReset JTAG/DMI
2020-12-14 Michael NeulingMerge pull request #256 from antonblanchard/flash-reset
2020-12-14 Paul MackerrasMerge pull request #257 from antonblanchard/nofpu-fix
2020-12-14 Anton BlanchardFix an issue in flash controller when BOOT_CLOCKS is...
2020-12-13 Anton BlanchardFully initialize FPU buses when FPU is disabled
2020-12-12 Anton BlanchardFix a few reset issues in flash controller
2020-12-08 Anton BlanchardMerge pull request #255 from antonblanchard/log-length
2020-12-08 Anton BlanchardMerge pull request #254 from antonblanchard/fix-verilator
2020-12-08 Anton BlanchardAdd LOG_LENGTH to top-generic.vhdl
2020-12-07 Anton BlanchardAdd verilator FPGA target
2020-12-07 Anton BlanchardMerge pull request #253 from antonblanchard/fix-verilator
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