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yosys.git
2015-08-09 Clifford WolfUse MEMID as name for $mem cell commit | commitdiff | tree
2015-08-06 Clifford WolfMerge pull request #69 from zeldin/master commit | commitdiff | tree
2015-08-06 Marcus ComstedtAdded iCE40 WARMBOOT cell commit | commitdiff | tree
2015-08-05 Clifford WolfRemove some very strange whitespace in btor.cc (by... commit | commitdiff | tree
2015-08-05 Clifford WolfBugfix in SMV back-end for partially unassigned wires commit | commitdiff | tree
2015-08-04 Clifford WolfAdded ENABLE_LIBYOSYS Makefile option commit | commitdiff | tree
2015-08-04 Clifford WolfAdded $assert support to SMV back-end commit | commitdiff | tree
2015-08-04 Clifford WolfAdded libyosys.so build commit | commitdiff | tree
2015-08-01 Clifford WolfMerge pull request #68 from zeldin/master commit | commitdiff | tree
2015-08-01 Marcus ComstedtAdd -noautowire option to verilog frontend commit | commitdiff | tree
2015-07-31 Clifford WolfAdded WORDS parameter to $meminit commit | commitdiff | tree
2015-07-30 Clifford WolfFixed flatten $meminit handling commit | commitdiff | tree
2015-07-29 Clifford WolfImprovements in BLIF back-end commit | commitdiff | tree
2015-07-29 Clifford WolfFixed nested mem2reg commit | commitdiff | tree
2015-07-27 Clifford WolfDon't write a 17th memory bit in ice40/cells_sim (by... commit | commitdiff | tree
2015-07-27 Clifford WolfFixed "check" command for inout ports commit | commitdiff | tree
2015-07-25 Clifford WolfSome cleanups in opt_rmdff commit | commitdiff | tree
2015-07-25 Clifford WolfAdded "miter -assert" commit | commitdiff | tree
2015-07-25 Clifford WolfKeep modules with $assume (like $assert) commit | commitdiff | tree
2015-07-24 Clifford WolfImproved $adff simplification commit | commitdiff | tree
2015-07-20 Clifford WolfiCE40 DFF sim models: init Q regs to 0 commit | commitdiff | tree
2015-07-18 Clifford WolfFixed techmap processes error msg commit | commitdiff | tree
2015-07-18 Clifford WolfAvoid tristate warning for blackbox ice40/cells_sim.v commit | commitdiff | tree
2015-07-16 Clifford WolfSome fixes in "select" command commit | commitdiff | tree
2015-07-10 Clifford WolfFixed YosysJS.create_worker() usage of this.url_prefix commit | commitdiff | tree
2015-07-06 Clifford WolfImproved liberty file test case commit | commitdiff | tree
2015-07-06 Clifford WolfUpdated ABC commit | commitdiff | tree
2015-07-06 Clifford WolfDo not collect disabled $memwr cells commit | commitdiff | tree
2015-07-04 Clifford WolfImproved YosysJS WebWorker API commit | commitdiff | tree
2015-07-03 Clifford WolfBugfix in fsm_extract commit | commitdiff | tree
2015-07-02 Clifford WolfAdded "synth -nofsm" commit | commitdiff | tree
2015-07-02 Clifford WolfFixed trailing whitespaces commit | commitdiff | tree
2015-07-01 Clifford WolfAdded opt_const -clkinv commit | commitdiff | tree
2015-06-30 Clifford WolfAdded logic-loop error handling to freduce commit | commitdiff | tree
2015-06-29 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys commit | commitdiff | tree
2015-06-29 Clifford WolfBugfix in chparam commit | commitdiff | tree
2015-06-29 Clifford WolfAdded design->rename(module, new_name) commit | commitdiff | tree
2015-06-28 Clifford WolfAdded YosysJS.create_worker() commit | commitdiff | tree
2015-06-20 Clifford WolfiCE40: set min bram efficiency to 2% commit | commitdiff | tree
2015-06-20 Clifford WolfUsing static mem size of 128 MB in emcc build commit | commitdiff | tree
2015-06-19 Clifford WolfAdded init support to SMV back-end commit | commitdiff | tree
2015-06-19 Clifford WolfProgress in SMV back-end commit | commitdiff | tree
2015-06-19 Clifford WolfProgress in SMV back-end commit | commitdiff | tree
2015-06-18 Clifford WolfProgress in SMV back-end commit | commitdiff | tree
2015-06-17 Clifford WolfProgress in SMV back-end commit | commitdiff | tree
2015-06-17 Clifford WolfAdded "rename -top new_name" commit | commitdiff | tree
2015-06-17 Clifford WolfProgress in SMV back-end commit | commitdiff | tree
2015-06-16 Clifford WolfProgress in SMV back-end commit | commitdiff | tree
2015-06-15 Clifford WolfAdded "synth -nordff -noalumacc" commit | commitdiff | tree
2015-06-15 Clifford WolfProgress in SMV back-end commit | commitdiff | tree
2015-06-15 Clifford WolfProgress in SMV back-end commit | commitdiff | tree
2015-06-14 Clifford WolfAdded "write_smv" skeleton commit | commitdiff | tree
2015-06-14 Clifford WolfRemoved debug code from write_smt2 commit | commitdiff | tree
2015-06-14 Clifford WolfModernized memory_dff (and fixed a bug) commit | commitdiff | tree
2015-06-14 Clifford WolfAdded "memory -nordff" commit | commitdiff | tree
2015-06-14 Clifford WolfAdded write_smt2 -mem commit | commitdiff | tree
2015-06-11 Clifford WolfMakefile fix for YosysJS build commit | commitdiff | tree
2015-06-11 Clifford WolfFixed cstr_buf for std::string with small string optimi... commit | commitdiff | tree
2015-06-11 Clifford WolfImprovements in cellaigs.cc and "json -aig" commit | commitdiff | tree
2015-06-10 Clifford WolfAigMaker refactoring commit | commitdiff | tree
2015-06-10 Clifford WolfAdded "json -aig" commit | commitdiff | tree
2015-06-10 Clifford WolfRenamed "aig" to "aigmap" commit | commitdiff | tree
2015-06-10 Clifford WolfFixed cellaigs port extending commit | commitdiff | tree
2015-06-09 Clifford WolfAdded "aig" pass commit | commitdiff | tree
2015-06-09 Clifford Wolfsynth_ice40 now flattens by default commit | commitdiff | tree
2015-06-09 Clifford WolfAdded cellaigs API commit | commitdiff | tree
2015-06-09 Clifford WolfMerge clock inverters in memory_dff commit | commitdiff | tree
2015-06-09 Clifford WolfMerge branch 'verilog-backend-memV2' of github.com... commit | commitdiff | tree
2015-06-08 luke whittlesey$mem cell in verilog backend : grouped writes by clock commit | commitdiff | tree
2015-06-08 Clifford WolfFixed "avail_parameters" handling in module clone/copy commit | commitdiff | tree
2015-06-08 Clifford WolfAdded log_dump() support for IdStrings commit | commitdiff | tree
2015-06-08 Clifford WolfFixed handling of parameters with reversed range commit | commitdiff | tree
2015-06-04 luke whittleseyBug fix in $mem verilog backend + changed tests/bram... commit | commitdiff | tree
2015-05-31 Clifford WolfAdded opt_share -share_all commit | commitdiff | tree
2015-05-31 Clifford WolfAdded iCE40 PLL cells commit | commitdiff | tree
2015-05-31 Clifford WolfAdded liberty dont_use support to dfflibmap commit | commitdiff | tree
2015-05-29 Clifford WolfFixed signedness of genvar expressions commit | commitdiff | tree
2015-05-26 Clifford WolfAdded output args to synth_ice40 commit | commitdiff | tree
2015-05-24 Clifford WolfImprovements in BLIF front-end commit | commitdiff | tree
2015-05-23 Clifford Wolfimproved ice40 SB_IO sim model commit | commitdiff | tree
2015-05-23 Clifford WolfImproved "flatten" handlings of inout ports commit | commitdiff | tree
2015-05-23 Clifford WolfAdded simple $dlatch support to opt_rmdff commit | commitdiff | tree
2015-05-23 Clifford WolfAdded ice40 SB_IO sim model commit | commitdiff | tree
2015-05-22 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys commit | commitdiff | tree
2015-05-22 Clifford Wolfpreserve used $-wires with init attribute in opt_clean commit | commitdiff | tree
2015-05-20 Clifford WolfSome fixes for $mem in verilog back-end commit | commitdiff | tree
2015-05-18 Clifford Wolfbugfix in blif front-end commit | commitdiff | tree
2015-05-17 Clifford Wolfadded vloghtb test_febe.sh commit | commitdiff | tree
2015-05-17 Clifford WolfImproved .latch support in BLIF front-end commit | commitdiff | tree
2015-05-17 Clifford WolfAdded read_blif command commit | commitdiff | tree
2015-05-17 Clifford WolfGeneralized blifparse API commit | commitdiff | tree
2015-05-17 Clifford Wolfabc/blifparse files reorganization commit | commitdiff | tree
2015-05-17 Clifford WolfVerific build fixes commit | commitdiff | tree
2015-05-13 Clifford WolfAdded .barbuf support to abc BLIF parser commit | commitdiff | tree
2015-05-11 Clifford Wolfchanged file() to open() in python scripts commit | commitdiff | tree
2015-05-11 Clifford WolfMerge pull request #63 from wluker/verilog-backend-mem commit | commitdiff | tree
2015-05-11 luke whittleseyFixed bug in $mem cell verilog code generation. commit | commitdiff | tree
2015-05-10 Clifford WolfDisabled broken $mem support in verilog backend commit | commitdiff | tree
2015-05-10 Clifford WolfMerge pull request #62 from wluker/verilog-backend-mem commit | commitdiff | tree
2015-05-10 luke whittleseyMade changes recommended by Clifford Wolf ... commit | commitdiff | tree
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