yosys.git
2015-08-09 Clifford WolfUse MEMID as name for $mem cell
2015-08-06 Clifford WolfMerge pull request #69 from zeldin/master
2015-08-06 Marcus ComstedtAdded iCE40 WARMBOOT cell
2015-08-05 Clifford WolfRemove some very strange whitespace in btor.cc (by...
2015-08-05 Clifford WolfBugfix in SMV back-end for partially unassigned wires
2015-08-04 Clifford WolfAdded ENABLE_LIBYOSYS Makefile option
2015-08-04 Clifford WolfAdded $assert support to SMV back-end
2015-08-04 Clifford WolfAdded libyosys.so build
2015-08-01 Clifford WolfMerge pull request #68 from zeldin/master
2015-08-01 Marcus ComstedtAdd -noautowire option to verilog frontend
2015-07-31 Clifford WolfAdded WORDS parameter to $meminit
2015-07-30 Clifford WolfFixed flatten $meminit handling
2015-07-29 Clifford WolfImprovements in BLIF back-end
2015-07-29 Clifford WolfFixed nested mem2reg
2015-07-27 Clifford WolfDon't write a 17th memory bit in ice40/cells_sim (by...
2015-07-27 Clifford WolfFixed "check" command for inout ports
2015-07-25 Clifford WolfSome cleanups in opt_rmdff
2015-07-25 Clifford WolfAdded "miter -assert"
2015-07-25 Clifford WolfKeep modules with $assume (like $assert)
2015-07-24 Clifford WolfImproved $adff simplification
2015-07-20 Clifford WolfiCE40 DFF sim models: init Q regs to 0
2015-07-18 Clifford WolfFixed techmap processes error msg
2015-07-18 Clifford WolfAvoid tristate warning for blackbox ice40/cells_sim.v
2015-07-16 Clifford WolfSome fixes in "select" command
2015-07-10 Clifford WolfFixed YosysJS.create_worker() usage of this.url_prefix
2015-07-06 Clifford WolfImproved liberty file test case
2015-07-06 Clifford WolfUpdated ABC
2015-07-06 Clifford WolfDo not collect disabled $memwr cells
2015-07-04 Clifford WolfImproved YosysJS WebWorker API
2015-07-03 Clifford WolfBugfix in fsm_extract
2015-07-02 Clifford WolfAdded "synth -nofsm"
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-07-01 Clifford WolfAdded opt_const -clkinv
2015-06-30 Clifford WolfAdded logic-loop error handling to freduce
2015-06-29 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-06-29 Clifford WolfBugfix in chparam
2015-06-29 Clifford WolfAdded design->rename(module, new_name)
2015-06-28 Clifford WolfAdded YosysJS.create_worker()
2015-06-20 Clifford WolfiCE40: set min bram efficiency to 2%
2015-06-20 Clifford WolfUsing static mem size of 128 MB in emcc build
2015-06-19 Clifford WolfAdded init support to SMV back-end
2015-06-19 Clifford WolfProgress in SMV back-end
2015-06-19 Clifford WolfProgress in SMV back-end
2015-06-18 Clifford WolfProgress in SMV back-end
2015-06-17 Clifford WolfProgress in SMV back-end
2015-06-17 Clifford WolfAdded "rename -top new_name"
2015-06-17 Clifford WolfProgress in SMV back-end
2015-06-16 Clifford WolfProgress in SMV back-end
2015-06-15 Clifford WolfAdded "synth -nordff -noalumacc"
2015-06-15 Clifford WolfProgress in SMV back-end
2015-06-15 Clifford WolfProgress in SMV back-end
2015-06-14 Clifford WolfAdded "write_smv" skeleton
2015-06-14 Clifford WolfRemoved debug code from write_smt2
2015-06-14 Clifford WolfModernized memory_dff (and fixed a bug)
2015-06-14 Clifford WolfAdded "memory -nordff"
2015-06-14 Clifford WolfAdded write_smt2 -mem
2015-06-11 Clifford WolfMakefile fix for YosysJS build
2015-06-11 Clifford WolfFixed cstr_buf for std::string with small string optimi...
2015-06-11 Clifford WolfImprovements in cellaigs.cc and "json -aig"
2015-06-10 Clifford WolfAigMaker refactoring
2015-06-10 Clifford WolfAdded "json -aig"
2015-06-10 Clifford WolfRenamed "aig" to "aigmap"
2015-06-10 Clifford WolfFixed cellaigs port extending
2015-06-09 Clifford WolfAdded "aig" pass
2015-06-09 Clifford Wolfsynth_ice40 now flattens by default
2015-06-09 Clifford WolfAdded cellaigs API
2015-06-09 Clifford WolfMerge clock inverters in memory_dff
2015-06-09 Clifford WolfMerge branch 'verilog-backend-memV2' of github.com...
2015-06-08 luke whittlesey$mem cell in verilog backend : grouped writes by clock
2015-06-08 Clifford WolfFixed "avail_parameters" handling in module clone/copy
2015-06-08 Clifford WolfAdded log_dump() support for IdStrings
2015-06-08 Clifford WolfFixed handling of parameters with reversed range
2015-06-04 luke whittleseyBug fix in $mem verilog backend + changed tests/bram...
2015-05-31 Clifford WolfAdded opt_share -share_all
2015-05-31 Clifford WolfAdded iCE40 PLL cells
2015-05-31 Clifford WolfAdded liberty dont_use support to dfflibmap
2015-05-29 Clifford WolfFixed signedness of genvar expressions
2015-05-26 Clifford WolfAdded output args to synth_ice40
2015-05-24 Clifford WolfImprovements in BLIF front-end
2015-05-23 Clifford Wolfimproved ice40 SB_IO sim model
2015-05-23 Clifford WolfImproved "flatten" handlings of inout ports
2015-05-23 Clifford WolfAdded simple $dlatch support to opt_rmdff
2015-05-23 Clifford WolfAdded ice40 SB_IO sim model
2015-05-22 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-05-22 Clifford Wolfpreserve used $-wires with init attribute in opt_clean
2015-05-20 Clifford WolfSome fixes for $mem in verilog back-end
2015-05-18 Clifford Wolfbugfix in blif front-end
2015-05-17 Clifford Wolfadded vloghtb test_febe.sh
2015-05-17 Clifford WolfImproved .latch support in BLIF front-end
2015-05-17 Clifford WolfAdded read_blif command
2015-05-17 Clifford WolfGeneralized blifparse API
2015-05-17 Clifford Wolfabc/blifparse files reorganization
2015-05-17 Clifford WolfVerific build fixes
2015-05-13 Clifford WolfAdded .barbuf support to abc BLIF parser
2015-05-11 Clifford Wolfchanged file() to open() in python scripts
2015-05-11 Clifford WolfMerge pull request #63 from wluker/verilog-backend-mem
2015-05-11 luke whittleseyFixed bug in $mem cell verilog code generation.
2015-05-10 Clifford WolfDisabled broken $mem support in verilog backend
2015-05-10 Clifford WolfMerge pull request #62 from wluker/verilog-backend-mem
2015-05-10 luke whittleseyMade changes recommended by Clifford Wolf ...
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