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nmigen.git
2019-08-03 whitequarkbuild.plat,vendor: automatically create sync domain... commit | commitdiff | tree
2019-08-03 whitequarkhdl.ir: allow adding more than one domain in missing... commit | commitdiff | tree
2019-08-03 whitequarkhdl.ir: don't expose as ports missing domains added... commit | commitdiff | tree
2019-08-03 whitequarkbuild.plat: add default_rst, to be used with default_clk. commit | commitdiff | tree
2019-08-03 whitequarkbuild.plat: add default_clk{,_constraint,_frequency}. commit | commitdiff | tree
2019-08-03 whitequarkhdl.ir: allow returning elaboratables from missing... commit | commitdiff | tree
2019-08-03 whitequarkhdl.ir: raise DomainError if a domain is used but not... commit | commitdiff | tree
2019-08-03 whitequarkhdl.ir: call back from Fragment.prepare if a clock... commit | commitdiff | tree
2019-08-03 whitequarkhdl.dsl: warn on suspicious statements like `m.If(... commit | commitdiff | tree
2019-08-03 whitequarkImprove test added in 29fee01f to not leak warnings. commit | commitdiff | tree
2019-08-03 whitequarkback.rtlil: fix sim-synth mismatch with assigns followi... commit | commitdiff | tree
2019-08-03 whitequarkhdl.ast: fix typo. commit | commitdiff | tree
2019-08-03 whitequarkhdl.ast: deprecate Value.part, add Value.{bit,word... commit | commitdiff | tree
2019-08-03 whitequarkhdl.ast, back.rtlil: add source locations to anonymous... commit | commitdiff | tree
2019-08-03 whitequarkhdl.ir: warn if .elaborate() returns None. commit | commitdiff | tree
2019-07-31 whitequarkhdl.xfrm: handle mem.{Read,Write}Port in CEInserter. commit | commitdiff | tree
2019-07-21 N. Engelhardtvendor: don't emit duplicate iobuf submodule names. commit | commitdiff | tree
2019-07-19 N. Engelhardthdl.dsl: add getters to m.submodules. commit | commitdiff | tree
2019-07-15 Alain Péteutlib.fifo: fix typo. commit | commitdiff | tree
2019-07-14 Staf VerhaegenPin: Add extra hierarchy level for name derivation commit | commitdiff | tree
2019-07-14 William D.... build.run: Ensure batch script returns proper error... commit | commitdiff | tree
2019-07-12 whitequarkback.pysim: correctly add gtkwave traces for signals... commit | commitdiff | tree
2019-07-10 William D.... build.dsl: Add optional name_suffix to Resource.family. commit | commitdiff | tree
2019-07-10 whitequarkback.pysim: avoid malformed VCD files when a decoder... commit | commitdiff | tree
2019-07-10 whitequarkhdl.ir: make UnusedElaboratable a real warning. commit | commitdiff | tree
2019-07-09 whitequarkback.rtlil: add decodings to cases when switching on... commit | commitdiff | tree
2019-07-09 whitequarkback.verilog: run proc_prune for much cleaner output. commit | commitdiff | tree
2019-07-09 whitequarkhdl.{ast,dsl},back.rtlil: track source locations for... commit | commitdiff | tree
2019-07-09 Jacob Lifshaytracer: add PyPy support to get_var_name(). commit | commitdiff | tree
2019-07-09 whitequarkbuild.dsl: add Resource.family abstraction. commit | commitdiff | tree
2019-07-08 whitequarkbuild.{dsl,res}: allow platform-dependent attributes... commit | commitdiff | tree
2019-07-08 whitequarkhdl.rec: respect modifications to signals in Record... commit | commitdiff | tree
2019-07-08 whitequarkback.rtlil: don't name-prefix signals connected to... commit | commitdiff | tree
2019-07-08 whitequarkbuild.{dsl,res}: allow removing attributes from subsignals. commit | commitdiff | tree
2019-07-08 whitequarkbuild.dsl: allow assertions on subsignal widths. commit | commitdiff | tree
2019-07-08 whitequarkhdl.{ast,cd,dsl,xfrm}: reject inappropriately used... commit | commitdiff | tree
2019-07-08 whitequarktest: fix Travis. commit | commitdiff | tree
2019-07-08 whitequarktest: generate examples to verilog as part of unit... commit | commitdiff | tree
2019-07-08 whitequarkexamples/basic/ctr_ce: fix outdated syntax. commit | commitdiff | tree
2019-07-08 whitequarkcompat.genlib.fsm: fix after commit dac62754. commit | commitdiff | tree
2019-07-08 whitequarkhdl.xfrm: don't overwrite source locations on ClockDoma... commit | commitdiff | tree
2019-07-08 whitequarkhdl.{dsl,mem,xfrm}: inject appropriate source locations. commit | commitdiff | tree
2019-07-08 whitequarkback.rtlil: ignore empty source locations. commit | commitdiff | tree
2019-07-08 whitequarkhdl.ast: use keyword-only arguments as appropriate. commit | commitdiff | tree
2019-07-08 whitequarkback.rtlil: attach source locations to switches, not... commit | commitdiff | tree
2019-07-08 whitequarkback.rtlil: use a more principled approach to attribute... commit | commitdiff | tree
2019-07-07 Alain Péteutvendor.xilinx_7series: generate also binary bitfile. commit | commitdiff | tree
2019-07-07 William D.... vendor.xilinx_spartan_3_6: Add Spartan3A family support. commit | commitdiff | tree
2019-07-07 whitequarkvendor.lattice_ecp5: don't leave LUT inputs disconnected. commit | commitdiff | tree
2019-07-07 whitequarkhdl.dsl: further clarify error message for incorrect... commit | commitdiff | tree
2019-07-07 whitequarkhdl.dsl: clarify error message for incorrect nesting. commit | commitdiff | tree
2019-07-07 whitequarkhdl.dsl: gracefully handle FSM with no states. commit | commitdiff | tree
2019-07-07 whitequarkbuild.plat: source a script with toolchain environment. commit | commitdiff | tree
2019-07-07 whitequarkbuild.run: only use os.path on the target OS. commit | commitdiff | tree
2019-07-07 whitequarkbuild.run: make BuildProducts abstract, add LocalBuildP... commit | commitdiff | tree
2019-07-06 whitequarkbuild.plat, vendor.*: don't join strings passed as... commit | commitdiff | tree
2019-07-06 whitequarkbuild.run: make sure BuildProducts._root is not easily... commit | commitdiff | tree
2019-07-04 Staf Verhaegenvendor.xilinx_{7series,spartan6}: Support extra VHDL... commit | commitdiff | tree
2019-07-03 whitequarkhdl.dsl: fix src_loc_at for FSM state signal. commit | commitdiff | tree
2019-07-03 whitequarkback.rtlil: emit \src attributes for processes via... commit | commitdiff | tree
2019-07-03 whitequarkhdl.ast: fix src_loc_at for Mux(). commit | commitdiff | tree
2019-07-03 whitequarkbuild.res: detect physical conflicts earlier. commit | commitdiff | tree
2019-07-03 whitequarkhdl.rec: thread src_loc_at to all inner Signals and... commit | commitdiff | tree
2019-07-03 whitequarkvendor: give names to IO buffer instances. commit | commitdiff | tree
2019-07-03 whitequarkhdl.rec: accept Record(src_loc_at=...). commit | commitdiff | tree
2019-07-03 whitequarkcompat.fhdl.specials: mark CompatMemory as Elaboratable. commit | commitdiff | tree
2019-07-03 whitequarkcompat.fhdl.specials: use "sync" as default domain... commit | commitdiff | tree
2019-07-03 whitequarkcompat.fhdl.specials: fix Memory.get_port() after 94e8f479. commit | commitdiff | tree
2019-07-03 whitequarkcompat.fhdl.structure: fix If/Elif/Else after 32446831. commit | commitdiff | tree
2019-07-03 Sebastien Bourdeauducqlattice_ecp5: fix get_input commit | commitdiff | tree
2019-07-02 whitequarkhdl.ast: recognize a Enum used as decoder and format... commit | commitdiff | tree
2019-07-02 whitequarkhdl.mem: fix naming of registers inside unnamed memories. commit | commitdiff | tree
2019-07-02 Alain Péteutbuild.plat: add iter_extra_files method. commit | commitdiff | tree
2019-07-02 whitequarkback.rtlil: emit \sig$next wires instead of \$next... commit | commitdiff | tree
2019-07-02 whitequarkback.rtlil: do not emit $next wires for comb signals. commit | commitdiff | tree
2019-07-02 whitequarkhdl.rec: implement slicing by component names. commit | commitdiff | tree
2019-07-02 whitequarkhdl.rec: implement Record.like. commit | commitdiff | tree
2019-07-02 Alain Péteutvendor.xilinx_7series: read extra .xdc files. commit | commitdiff | tree
2019-07-01 whitequarkhdl.mem: use read_port(domain="comb") for asynchronous... commit | commitdiff | tree
2019-07-01 whitequarkback.rtlil: fix Array regression in 32446831. commit | commitdiff | tree
2019-06-28 whitequarkback.pysim: create unique ResetSynchronizer internal... commit | commitdiff | tree
2019-06-28 whitequarkback.pysim: override ResetSynchronizer implementation. commit | commitdiff | tree
2019-06-28 whitequarklib.cdc: avoid interior clock domains in ResetSynchronizer. commit | commitdiff | tree
2019-06-28 whitequarklib.cdc: eliminate no_retiming attributes. commit | commitdiff | tree
2019-06-28 whitequarkvendor.lattice_ice40: fix instance of negedge FF due... commit | commitdiff | tree
2019-06-28 Alain Péteutbuild.plat: fix dedent overrides. commit | commitdiff | tree
2019-06-28 whitequarkREADME: tone down the instability warning to reflect... commit | commitdiff | tree
2019-06-28 whitequarkhdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case... commit | commitdiff | tree
2019-06-28 whitequarkhdl.ir, back.rtlil: allow specifying attributes on... commit | commitdiff | tree
2019-06-27 whitequarkexamples: add concise UART example. commit | commitdiff | tree
2019-06-26 whitequarkback.pysim: fix scope screwup. commit | commitdiff | tree
2019-06-25 whitequarkcompat.fhdl.structure: fix typo. commit | commitdiff | tree
2019-06-25 whitequarkcompat.fhdl.structure: simplify handling of default... commit | commitdiff | tree
2019-06-25 whitequarkhdl.{ast,dst}: directly represent RTLIL default case. commit | commitdiff | tree
2019-06-25 whitequarkvendor.xilinx_{spartan6,7series}: speedgrade→speed. commit | commitdiff | tree
2019-06-25 whitequarkvendor.lattice_ecp5: implement. commit | commitdiff | tree
2019-06-24 Sebastien BourdeauducqREADME: update nMigen libs paragraph commit | commitdiff | tree
2019-06-24 Sebastien BourdeauducqREADME: add clarification about HLS commit | commitdiff | tree
2019-06-19 whitequarkvendor.lattice_ice40: use different --package for 4k... commit | commitdiff | tree
2019-06-17 Jean-François... vendor.xilinx_7series: fix IOB packing. commit | commitdiff | tree
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