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yosys.git
2019-04-03
Eddie Hung
Disable shregmap in synth_xilinx if -retime
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2019-04-03
Eddie Hung
Add changelog entry
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2019-04-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-03
Clifford Wolf
Merge pull request #912 from YosysHQ/bram_addr_en
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2019-04-03
Clifford Wolf
Merge pull request #910 from ucb-bar/memupdates
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2019-04-02
David Shah
memory_bram: Consider read enable for address expansion...
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2019-04-02
Eddie Hung
Merge pull request #895 from YosysHQ/pmux2shiftx
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2019-04-01
Jim Lawson
Refine memory support to deal with general Verilog...
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2019-03-29
Clifford Wolf
Merge pull request #907 from YosysHQ/clifford/fix906
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2019-03-29
Clifford Wolf
Build Verilog parser with -DYYMAXDEPTH=100000, fixes...
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2019-03-28
Clifford Wolf
Merge pull request #901 from trcwm/libertyfixes
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2019-03-28
Clifford Wolf
Merge pull request #903 from YosysHQ/bram_reset_transp
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2019-03-27
David Shah
memory_bram: Reset make_transp when growing read ports
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2019-03-27
Niels Moseley
Liberty file parser now accepts superfluous ;
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2019-03-27
Niels Moseley
Liberty file parser now accepts superfluous ;
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2019-03-27
Niels Moseley
Liberty file parser now accepts superfluous ;
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2019-03-27
Clifford Wolf
Add "read -verific" and "read -noverific"
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2019-03-27
Clifford Wolf
Add "rename -output"
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2019-03-27
Clifford Wolf
Improve "rename" help message
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2019-03-26
Clifford Wolf
Add "cutpoint -undef"
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2019-03-26
Clifford Wolf
Add "hdlname" attribute
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2019-03-26
Clifford Wolf
Fix "verific -extnets" for more complex situations
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2019-03-25
Eddie Hung
synth_xilinx to use shregmap with -minlen 3
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2019-03-25
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-25
Clifford Wolf
Add "cutpoint" pass
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2019-03-25
Eddie Hung
Create one $shiftx per bit in width
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2019-03-25
Clifford Wolf
Merge pull request #896 from YosysHQ/transp_fixes
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2019-03-25
Clifford Wolf
Merge pull request #897 from trcwm/libertyfixes
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2019-03-25
Niels Moseley
spaces -> tabs
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2019-03-25
Niels Moseley
EOL is now accepted as ';' replacement on lines that...
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2019-03-24
Niels Moseley
Updated the liberty parser to accept [A:B] ranges ...
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2019-03-24
David Shah
memory_bram: Fix multiclock make_transp
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2019-03-23
Eddie Hung
Add a pmux-to-shiftx optimisation to proc_mux
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2019-03-23
Eddie Hung
Cope with SHREG not having E port; Revert $pmux fine...
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2019-03-23
Clifford Wolf
Add "mutate -none -mode", "mutate -mode none"
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2019-03-23
Clifford Wolf
Add "mutate -s <filename>"
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2019-03-23
Clifford Wolf
Merge pull request #893 from YosysHQ/clifford/btormeminit
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2019-03-23
Clifford Wolf
Add support for memory initialization to write_btor
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2019-03-23
Clifford Wolf
Fix BTOR output tags syntax in writye_btor
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2019-03-23
Clifford Wolf
Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend...
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2019-03-23
Eddie Hung
Add support for SHREGMAP+$mux, also fine tune $pmux
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2019-03-23
Eddie Hung
Leftover printf
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2019-03-23
Eddie Hung
Fixes for multibit
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2019-03-23
Eddie Hung
Working for 1 bit
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2019-03-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-22
Clifford Wolf
Merge pull request #889 from YosysHQ/clifford/fix888
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2019-03-22
Clifford Wolf
Merge pull request #890 from YosysHQ/clifford/fix887
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2019-03-22
David Shah
Merge pull request #891 from YosysHQ/xilinx_keep
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2019-03-22
David Shah
xilinx: Add keep attribute where appropriate
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2019-03-22
Clifford Wolf
Trim init attributes when resizing FFs in "wreduce...
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2019-03-21
Eddie Hung
Add '-nosrl' option to synth_xilinx
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2019-03-21
Clifford Wolf
Fix mem2reg handling of memories with upto data ports...
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2019-03-21
Clifford Wolf
Improve "read_verilog -dump_vlog[12]" handling of upto...
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2019-03-21
Clifford Wolf
Improve read_verilog debug output capabilities
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2019-03-21
Eddie Hung
Opt
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2019-03-20
Eddie Hung
Fix spacing
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2019-03-20
Eddie Hung
Fine tune cells_map.v
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2019-03-20
Eddie Hung
Revert $__SHREG_ to orig; use $__XILINX_SHREG for varia...
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2019-03-20
Eddie Hung
Add support for variable length Xilinx SRL > 128
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2019-03-19
Eddie Hung
Restore original synth_xilinx commands
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2019-03-19
Eddie Hung
Fix spacing
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2019-03-19
Eddie Hung
shregmap -tech xilinx to delete $shiftx for var length SRL
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2019-03-19
Eddie Hung
Fix INIT for variable length SRs that have been bumped...
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2019-03-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-19
Eddie Hung
Make output port a non chain user
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2019-03-19
Clifford Wolf
Merge pull request #885 from YosysHQ/clifford/fix873
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2019-03-19
Clifford Wolf
Add Xilinx negedge FFs to synth_xilinx dffinit call...
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2019-03-19
Eddie Hung
Merge pull request #808 from eddiehung/read_aiger
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2019-03-19
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-03-19
Eddie Hung
Add author name
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2019-03-19
Clifford Wolf
Merge pull request #884 from zachjs/master
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2019-03-19
Zachary Snow
fix local name resolution in prefix constructs
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2019-03-18
Eddie Hung
Fix shregmap to correctly recognise non chain users...
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2019-03-18
Eddie Hung
shiftx NULL pointer check
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2019-03-17
Clifford Wolf
Update issue template
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2019-03-17
Clifford Wolf
Update issue template
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2019-03-16
Eddie Hung
Cleanup
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2019-03-16
Eddie Hung
Only accept <128 for variable length, only if $shiftx...
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2019-03-16
Clifford Wolf
Merge pull request #877 from FelixVi/master
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2019-03-16
Felix Vietmeyer
Add note about test requirements in README
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2019-03-16
Eddie Hung
Cleanup synth_xilinx
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2019-03-16
Eddie Hung
Working
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2019-03-15
Clifford Wolf
Improve mix of src/wire/wirebit coverage in "mutate...
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2019-03-15
Clifford Wolf
Merge pull request #876 from YosysHQ/clifford/fmcombine
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2019-03-15
Clifford Wolf
Add "fmcombine -fwd -bwd -nop"
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2019-03-15
Clifford Wolf
Add fmcombine pass
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2019-03-14
Clifford Wolf
Merge pull request #875 from YosysHQ/clifford/mutate
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2019-03-14
Clifford Wolf
Disable realmath tests
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2019-03-14
Clifford Wolf
Improvements in "mutate" list-reduce algorithm
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2019-03-14
Clifford Wolf
Add "mutate -cfg", improve pick_cover behavior
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2019-03-14
Clifford Wolf
Add a strictly coverage-driven mutation selection strategy
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2019-03-14
Clifford Wolf
Improve "mutate" wire coverage metric
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2019-03-14
Clifford Wolf
Add more mutation types, improve mutation src cover
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2019-03-14
Clifford Wolf
Fix smtbmc.py handling of zero appended steps
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2019-03-14
Clifford Wolf
Add "mutate" command DB reduce functionality
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2019-03-14
Clifford Wolf
Add hashlib "<container>::element(int n)" methods
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2019-03-14
Clifford Wolf
Add "mutate -mode inv", various other mutate improvements
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2019-03-14
Clifford Wolf
Add basic "mutate -list N" framework
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2019-03-14
Clifford Wolf
Merge pull request #874 from YosysHQ/clifford/andopt
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2019-03-14
Clifford Wolf
Improve handling of and-with-1 and or-with-0 in opt_exp...
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