yosys.git
2017-02-01 Clifford WolfUpdate ABC scripts to use "&nf" instead of "map"
2017-01-31 Clifford WolfMerge branch 'C-Elegans-opt_compare_pr'
2017-01-31 Clifford WolfFix indenting and log messages in code merged from...
2017-01-31 Clifford WolfMerge branch 'opt_compare_pr' of https://github.com...
2017-01-31 Clifford WolfImprove opt_rmdff support for $dlatch cells
2017-01-30 C-ElegansRefactor and generalize the comparision optimization
2017-01-30 Clifford WolfAdd "yosys-smtbmc --aig <aim_filename>:<aiw_filename...
2017-01-30 Clifford WolfAdd $ff and $_FF_ support to equiv_simple
2017-01-28 Clifford WolfAdd "yosys-smtbmc --aig-noheader" and AIGER mem init...
2017-01-26 Clifford WolfBe more conservative with merging large cells into...
2017-01-26 Clifford WolfAdd warnings for quickly growing FSM table size in...
2017-01-26 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-01-25 Clifford WolfFix RTLIL::Memory::start_offset initialization
2017-01-21 C-ElegansDo not use b.as_int() in calculation of bit set
2017-01-17 Clifford WolfAdd "enum" and "typedef" lexer support
2017-01-16 C-ElegansOptimize compares to powers of 2
2017-01-16 Clifford WolfMerge pull request #293 from thoughtpolice/minor-cleanup
2017-01-15 Austin Seipppasses/hierarchy: delete some dead code
2017-01-15 C-ElegansFix issue #269, optimize signed compare with 0
2017-01-15 Clifford WolfFix bug in AstNode::mem2reg_as_needed_pass2()
2017-01-11 Clifford WolfFix $initstate handling bug in yosys-smtbmc
2017-01-11 Clifford WolfUpdate ABC to hg id f8cadfe3861f
2017-01-08 Clifford WolfUpdated ABC to hg id 38b26a543f1d
2017-01-05 Clifford WolfFixed handling of local memories in functions
2017-01-04 Clifford WolfAdded "check -initdrv"
2017-01-04 Clifford WolfAdded handling of local memories and error for local...
2017-01-04 Clifford WolfImplicitly set "yosys-smtbmc --noprogress" on windows
2017-01-04 Clifford WolfFixed typo in tests/simple/arraycells.v
2017-01-04 Clifford WolfFixed "yosys-smtbmc --noprogress"
2017-01-03 Clifford WolfAdded Verilog $rtoi and $itor support
2017-01-02 Clifford WolfHandle "always 1" like "always -1" in .smtc files
2017-01-01 Clifford WolfAdded cell port resizing to hierarchy pass
2016-12-31 Clifford WolfUpdated ABC to hg id 55cd83f432c0
2016-12-31 Clifford WolfBugfix in RTLIL::SigSpec::remove2()
2016-12-29 Clifford WolfUpdated ABC to hg id 8c6a635f7a20
2016-12-29 Clifford WolfImproved write_json help message
2016-12-26 Clifford WolfUpdated ABC to hg id f591c081d5e7
2016-12-24 Clifford WolfMerge pull request #284 from azonenberg/master
2016-12-23 Andrew ZonenbergMerge pull request #1 from azonenberg-hk/master
2016-12-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-12-23 Clifford WolfSimplified log_spacer() code
2016-12-22 Clifford WolfAdded "yosys -W regex"
2016-12-21 Clifford WolfAdded AIGER back-end to automatic back-end detection
2016-12-21 Clifford WolfUpdated ABC to hg rev a4872e22c646
2016-12-21 Clifford WolfUpdated ABC to hg rev 8bab2eedbba4
2016-12-21 Andrew Zonenberggreenpak4: Added INT pin to GP_SPI
2016-12-21 Andrew Zonenberggreenpak4: removed unused MISO pin from GP_SPI
2016-12-20 Andrew Zonenberggreenpak4: Removed SPI_BUFFER parameter
2016-12-20 Andrew Zonenberggreenpak4: replaced MOSI/MISO with single one-way SDAT pin
2016-12-20 Andrew Zonenberggreenpak4: Changed port names on GP_SPI for clarity
2016-12-20 Andrew Zonenberggreenpak4: Initial implementation of GP_SPI cell
2016-12-17 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-12-17 Andrew Zonenberggreenpak4: Updated GP_DCMP cell model
2016-12-16 Andrew Zonenberggreenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.
2016-12-15 Clifford WolfAdded "verilog_defines" command
2016-12-15 Andrew Zonenberggreenpak4: Initial version of GP_DCMP skeleton (not...
2016-12-14 Andrew Zonenberggreenpak4: More fixups of GP_DCMPx cells
2016-12-14 Andrew Zonenberggreenpak4: And another typo :(
2016-12-14 Andrew Zonenberggreenpak4: Fixed another typo
2016-12-14 Andrew Zonenberggreenpak4: Fixed typo
2016-12-14 Andrew Zonenberggreenpak4: Cleaned up trailing spaces in cells_sim
2016-12-14 Andrew Zonenberggreenpak4: Added GP_DCMPREF / GP_DCMPMUX
2016-12-13 Clifford WolfBugfix in comment handling
2016-12-12 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-12-11 Clifford WolfAdded $anyconst support to AIGER back-end
2016-12-11 Clifford WolfMerge branch 'LSS-USP-unit-test-structure'
2016-12-11 Clifford WolfSome minor CodingReadme changes in unit test section
2016-12-11 Clifford WolfBuild hotfix in tests/unit/Makefile
2016-12-11 Andrew ZonenbergAdded GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF
2016-12-10 rodrigosiqueiraImproved unit test structure
2016-12-10 Andrew Zonenberggreenpak4: Added support for inferred input/output...
2016-12-10 Andrew Zonenberggreenpak4: Can now techmap inferred D latches (without...
2016-12-10 Andrew Zonenberggreenpak4: Inverted D latch cells now have nQ instead...
2016-12-06 Andrew ZonenbergAdded GP_DLATCH and GP_DLATCHI
2016-12-06 Andrew ZonenbergInitial implementation of techlib support for GreenPAK...
2016-12-06 Andrew ZonenbergUpdated help text for synth_greenpak4
2016-12-04 rodrigosiqueiraAdded explanation about configure and create test
2016-12-04 rodrigosiqueiraAdded required structure to implement unit tests
2016-12-03 Clifford WolfAdded $assert/$assume support to AIGER back-end
2016-12-03 Clifford WolfImproved yosys-smtbmc default -t/--assume-skipped for...
2016-12-01 Clifford WolfUpdated ABV to hg rev 8b555d9e67cf
2016-12-01 Clifford WolfAdded examples/aiger/
2016-12-01 Clifford WolfAdded "yosys-smtbmc --aig"
2016-12-01 Clifford WolfAdded support for partially initialized regs to smt2...
2016-12-01 Clifford WolfAdded "write_aiger -zinit -symbols -vmap"
2016-11-30 Clifford WolfAdded "write_aiger" command
2016-11-30 Clifford WolfAdded "design -reset-vlog"
2016-11-29 Clifford WolfImproved equiv_purge log output
2016-11-28 Clifford WolfBugfix in smt2 back-end for pure checker modules
2016-11-28 Clifford WolfAdded support for macros as include file names
2016-11-28 Clifford WolfBugfix in "read_verilog -D NAME=VAL" handling
2016-11-27 Clifford WolfRemoved shebang line from smtio.py, fixes #279
2016-11-23 Clifford WolfAdded wire start_offset and upto handling BLIF back-end
2016-11-23 Clifford WolfAdded wire start_offset and upto handling to splitnets cmd
2016-11-22 Clifford WolfMerge pull request #274 from oldtopman/lcurses
2016-11-22 Clifford WolfAdded "yosys-smtbmc --append"
2016-11-22 oldtopmanAdded optional flag for linking curses with readline.
2016-11-19 Clifford WolfMerge pull request #272 from AlexDaniel/master
2016-11-19 Aleks-Daniel... Keep lines under 80 characters
2016-11-19 Clifford WolfImproved ABC default scripts
next