microwatt.git
2019-09-12 Anton BlanchardAdd a simple direct mapped icache
2019-09-12 Anton BlanchardSOC memory wishbone should clear ACK regardless of STB
2019-09-12 Anton BlanchardMerge pull request #48 from antonblanchard/clk_gen_bypass
2019-09-12 Anton BlanchardFix clk_gen_bypass
2019-09-11 Anton BlanchardMerge pull request #47 from antonblanchard/if-fix
2019-09-11 Anton BlanchardMerge pull request #46 from antonblanchard/record-fix
2019-09-11 Anton BlanchardExplicitly check against '1' in if statements
2019-09-11 Anton BlanchardRemove names from end record statements
2019-09-11 Anton BlanchardMerge pull request #45 from antonblanchard/fixes
2019-09-11 Anton BlanchardFix issue in loadstore1
2019-09-11 Anton BlanchardFix issue in execute2
2019-09-11 Anton BlanchardMerge pull request #44 from antonblanchard/nia-remove
2019-09-11 Anton BlanchardRemove nia from loadstore and multiply
2019-09-11 Anton BlanchardMerge pull request #43 from mikey/trivial
2019-09-11 Michael NeulingRemove FIXME comment
2019-09-11 Anton BlanchardMerge pull request #41 from mikey/travis
2019-09-11 Anton BlanchardMerge pull request #42 from antonblanchard/fetch-rework-v2
2019-09-11 Anton BlanchardReformat core.vhdl
2019-09-11 Anton BlanchardRemove sim console
2019-09-11 Anton BlanchardReduce multiply to 2 cycles
2019-09-11 Anton BlanchardRegister outputs on writeback
2019-09-11 Anton BlanchardRegister outputs on execute2
2019-09-11 Anton BlanchardRegister outputs on loadstore1
2019-09-11 Anton BlanchardMove debug execute output into decode2
2019-09-11 Anton BlanchardRework pipeline, add stall and flush signals
2019-09-11 Michael NeulingAllow a full make check on Travis
2019-09-10 Anton BlanchardMerge pull request #40 from antonblanchard/makefile...
2019-09-10 Anton BlanchardUpdate Makefile dependencies
2019-09-10 Benjamin HerrenschmidtSwitch soc to use std_ulogic
2019-09-10 Benjamin HerrenschmidtShare soc.vhdl between FPGA and sim
2019-09-10 Benjamin HerrenschmidtPass wishbone record to bram memory module
2019-09-10 Benjamin HerrenschmidtRework wishbone slave address decoding
2019-09-10 Benjamin HerrenschmidtMove wishbone arbiter out of the core
2019-09-10 Benjamin HerrenschmidtRe-indent and reformat soc.vhdl
2019-09-10 Benjamin HerrenschmidtSplit FPGA toplevel from soc
2019-09-10 Anton BlanchardMerge pull request #39 from antonblanchard/no-x-state
2019-09-10 Anton BlanchardDon't send out X state from the memory behavioural
2019-09-10 Anton BlanchardMerge pull request #36 from mikey/gitignore
2019-09-10 Anton BlanchardMerge pull request #38 from antonblanchard/multiply...
2019-09-10 Anton BlanchardQuieten multiply warning
2019-09-10 Michael NeulingAdd new files to git ignore
2019-09-09 Anton BlanchardMerge pull request #35 from antonblanchard/multiply-opt
2019-09-09 Anton BlanchardSimplify multiply
2019-09-09 Anton BlanchardMerge pull request #34 from antonblanchard/decode-table
2019-09-09 Anton BlanchardAdd a decode bit to mark an instruction as single throu...
2019-09-09 Benjamin Herrenschmidtdecode1 array fix header
2019-09-09 Anton BlanchardMerge pull request #33 from antonblanchard/cr-fix
2019-09-09 Anton BlanchardMerge pull request #32 from antonblanchard/register...
2019-09-09 Benjamin HerrenschmidtUse simulated UART in core test bench
2019-09-09 Benjamin HerrenschmidtMake sim poll non-blocking
2019-09-09 Benjamin HerrenschmidtAdd simulated UART design
2019-09-09 Anton BlanchardFix CR forwarding
2019-09-09 Anton BlanchardAdd forwarding in the register file
2019-09-09 Anton BlanchardMerge pull request #31 from antonblanchard/no-second...
2019-09-09 Anton BlanchardMerge pull request #30 from antonblanchard/writeback...
2019-09-09 Anton BlanchardMore second write port removal
2019-09-09 Anton BlanchardAdd some assertions to writeback
2019-09-09 Anton BlanchardMerge pull request #29 from antonblanchard/no-second...
2019-09-09 Anton BlanchardMerge pull request #28 from antonblanchard/loadstore...
2019-09-09 Anton BlanchardRemove second write port
2019-09-09 Anton BlanchardRemove some more loadstore debug
2019-09-09 Anton BlanchardMerge pull request #27 from antonblanchard/fix-cr
2019-09-09 Anton BlanchardFix issues with CR rework
2019-09-09 Anton BlanchardMerge pull request #26 from antonblanchard/silence...
2019-09-09 Anton BlanchardMerge pull request #25 from antonblanchard/register_fil...
2019-09-09 Anton BlanchardMerge pull request #24 from antonblanchard/cr_file_cleanup
2019-09-09 Anton BlanchardSilence some loadstore related debug
2019-09-09 Anton BlanchardClean up register read debug output
2019-09-09 Anton BlanchardRework CR file and add forwarding
2019-09-08 Anton BlanchardMerge pull request #19 from antonblanchard/cmod-a7
2019-09-08 Anton BlanchardCmod A7-35 support
2019-09-08 Anton BlanchardMerge pull request #20 from antonblanchard/reset-rework2
2019-09-08 Anton BlanchardMerge pull request #22 from antonblanchard/store-fix
2019-09-08 Anton BlanchardStores need to wait for wishbone write ack
2019-09-08 Anton BlanchardMerge pull request #21 from antonblanchard/xdc-update
2019-09-07 Anton BlanchardAdd CONFIG_VOLTAGE and CFGBVS entries
2019-09-07 Anton BlanchardRework SOC reset
2019-09-07 Anton BlanchardRename a few reset signals
2019-09-06 Anton BlanchardMerge pull request #18 from mikey/verific
2019-09-06 Michael NeulingFix verific script with new VHDL files
2019-09-06 Anton BlanchardMerge pull request #17 from antonblanchard/writeback...
2019-09-05 Anton BlanchardUse a better input signal in writeback
2019-09-03 Anton BlanchardMerge pull request #16 from antonblanchard/decode2_rework2
2019-09-03 Anton BlanchardRework decode2
2019-08-31 Anton BlanchardMerge pull request #13 from mikey/dynamic-ranges
2019-08-30 Michael NeulingRemove dynamic ranges from code
2019-08-29 Anton BlanchardMerge pull request #10 from antonblanchard/arty-fix
2019-08-29 Anton BlanchardArty A7 reset pin is C2
2019-08-29 Anton BlanchardMerge pull request #7 from riktw/fusesoc_arty_a7
2019-08-29 Anton BlanchardMerge pull request #9 from antonblanchard/travis-fix
2019-08-29 Anton BlanchardA few Travis CI fixes
2019-08-29 riktwAdded support for building for Arty A7 boards
2019-08-28 Anton BlanchardMerge pull request #5 from antonblanchard/travis-test
2019-08-28 Anton BlanchardAdd an initial travis.yml
2019-08-28 Anton BlanchardAdd srd and srw
2019-08-28 Anton BlanchardAdd sim only divw
2019-08-27 Anton BlanchardFix ghdl build error with pp_soc_memory
2019-08-27 Anton Blanchardmicropython only requires 512kB of BRAM
2019-08-27 Anton BlanchardMerge pull request #6 from mikey/gif
2019-08-27 Anton BlanchardAdd -Wall to CFLAGS
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