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yosys.git
2019-12-19 Marcin Kościelnickixilinx: Add simulation models for remaining CLB primitives. commit | commitdiff | tree
2019-12-19 Marcin Kościelnickixilinx_dffopt: Keep order of LUT inputs. commit | commitdiff | tree
2019-12-18 Eddie HungAdd "scratchpad" to CHANGELOG commit | commitdiff | tree
2019-12-18 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys commit | commitdiff | tree
2019-12-18 David ShahMerge pull request #1563 from YosysHQ/dave/async-prld commit | commitdiff | tree
2019-12-18 Eddie HungMerge pull request #1572 from nakengelhardt/scratchpad_pass commit | commitdiff | tree
2019-12-18 Eddie HungMerge pull request #1584 from YosysHQ/mwk/xilinx-flaky... commit | commitdiff | tree
2019-12-18 Marcin Kościelnickitests/xilinx: fix flaky mux test commit | commitdiff | tree
2019-12-18 Marcin Kościelnickixilinx: Add xilinx_dffopt pass (#1557) commit | commitdiff | tree
2019-12-18 Marcin Kościelnickixilinx: Improve flip-flop handling. commit | commitdiff | tree
2019-12-18 Clifford WolfSend people to symbioticeda.com instead of verific.com commit | commitdiff | tree
2019-12-18 N. Engelhardtuse extra_args commit | commitdiff | tree
2019-12-17 Eddie HungCleanup commit | commitdiff | tree
2019-12-17 Eddie HungMerge pull request #1574 from YosysHQ/eddie/xilinx_lutram commit | commitdiff | tree
2019-12-17 Eddie HungMerge pull request #1521 from dh73/diego/memattr commit | commitdiff | tree
2019-12-17 Eddie HungEnforce non-existence commit | commitdiff | tree
2019-12-16 Eddie HungUpdate doc commit | commitdiff | tree
2019-12-16 Eddie HungAdd another test commit | commitdiff | tree
2019-12-16 Eddie HungMore sloppiness, thanks @dh73 for spotting commit | commitdiff | tree
2019-12-16 Eddie HungAccidentally commented out tests commit | commitdiff | tree
2019-12-16 Eddie HungAdd unconditional match blocks for force RAM commit | commitdiff | tree
2019-12-16 Eddie HungOops commit | commitdiff | tree
2019-12-16 Eddie HungMerge blockram tests commit | commitdiff | tree
2019-12-16 Eddie HungUpdate xc7/xcu bram rules commit | commitdiff | tree
2019-12-16 Eddie HungImplement 'attributes' grammar commit | commitdiff | tree
2019-12-16 Eddie HungMerge branch 'diego/memattr' of https://github.com... commit | commitdiff | tree
2019-12-16 Eddie HungMerge branch 'eddie/xilinx_lutram' of github.com:YosysH... commit | commitdiff | tree
2019-12-16 Eddie HungPopulate DID/DOD even if unused commit | commitdiff | tree
2019-12-16 Eddie HungRename *RAM{32,64}M rules to RAM{32X2,64X1}Q commit | commitdiff | tree
2019-12-16 Diego HFixing compiler warning/issues. Moving test script... commit | commitdiff | tree
2019-12-16 N. Engelhardtadd assert option to scratchpad command commit | commitdiff | tree
2019-12-16 Diego HRemoving fixed attribute value to !ramstyle rules commit | commitdiff | tree
2019-12-16 Diego HMerging attribute rules into a single match block;... commit | commitdiff | tree
2019-12-16 Eddie HungMerge pull request #1575 from rodrigomelo9/master commit | commitdiff | tree
2019-12-16 Eddie HungMerge pull request #1577 from gromero/for-yosys commit | commitdiff | tree
2019-12-16 Eddie HungMerge pull request #1578 from noopwafel/eqneq-debug commit | commitdiff | tree
2019-12-15 Alyssa MilburnFix opt_expr.eqneq.cmpzero debug print commit | commitdiff | tree
2019-12-13 Diego HRefactoring memory attribute matching based on IEEE... commit | commitdiff | tree
2019-12-13 Eddie HungMerge pull request #1533 from dh73/bram_xilinx commit | commitdiff | tree
2019-12-13 Eddie HungDisable RAM16X1D test commit | commitdiff | tree
2019-12-13 Eddie HungDisable RAM16X1D match rule; carry-over from LUT4 arches commit | commitdiff | tree
2019-12-13 Eddie HungRAM64M8 to also have [5:0] for address commit | commitdiff | tree
2019-12-13 Diego HRenaming BRAM memory tests for the sake of uniformity commit | commitdiff | tree
2019-12-13 Rodrigo Alejandro... Fixed some missing "verilog_" in documentation commit | commitdiff | tree
2019-12-13 N. Engelhardtadd periods and newlines to help message commit | commitdiff | tree
2019-12-13 Eddie HungRemove extraneous synth_xilinx call commit | commitdiff | tree
2019-12-13 Eddie HungAdd tests for these new models commit | commitdiff | tree
2019-12-13 Eddie HungAdd RAM32X6SDP and RAM64X3SDP modes commit | commitdiff | tree
2019-12-13 Eddie HungFix RAM64M model to have 6 bit address bus commit | commitdiff | tree
2019-12-13 Eddie HungAdd #1460 testcase commit | commitdiff | tree
2019-12-13 Eddie HungAdd memory rules for RAM16X1D, RAM32M, RAM64M commit | commitdiff | tree
2019-12-13 Eddie HungRename memory tests to lutram, add more xilinx tests commit | commitdiff | tree
2019-12-12 Diego HFixing citation in xc7_xcu_brams.txt file. Fixing RAMB3... commit | commitdiff | tree
2019-12-12 Eddie Hungabc9_map.v: fix Xilinx LUTRAM commit | commitdiff | tree
2019-12-12 Diego HAdding a note (TODO) in the memory_params.ys check... commit | commitdiff | tree
2019-12-12 N. Engelhardtadd test and make help message more verbose commit | commitdiff | tree
2019-12-12 Diego HUpdating RAMB36E1 thresholds. Adding test for both... commit | commitdiff | tree
2019-12-12 Diego HMerge https://github.com/YosysHQ/yosys into bram_xilinx commit | commitdiff | tree
2019-12-12 N. Engelhardtadd a command to read/modify scratchpad contents commit | commitdiff | tree
2019-12-12 Eddie HungUpdate README.md :: abc_ -> abc9_ commit | commitdiff | tree
2019-12-11 Eddie HungFix bitwidth mismatch; suppresses iverilog warning commit | commitdiff | tree
2019-12-11 Gustavo Romeromanual: Fix text in Abstract section commit | commitdiff | tree
2019-12-11 David ShahMerge pull request #1564 from ZirconiumX/intel_housekeeping commit | commitdiff | tree
2019-12-10 Dan Ravensloftsynth_intel: a10gx -> arria10gx commit | commitdiff | tree
2019-12-10 Dan Ravensloftsynth_intel: cyclone10 -> cyclone10lp commit | commitdiff | tree
2019-12-10 Eddie HungMerge pull request #1545 from YosysHQ/eddie/ice40_wrapc... commit | commitdiff | tree
2019-12-09 Eddie Hungice40_opt to restore attributes/name when unwrapping commit | commitdiff | tree
2019-12-09 Eddie Hungice40_wrapcarry -unwrap to preserve 'src' attribute commit | commitdiff | tree
2019-12-09 Eddie Hungunmap $__ICE40_CARRY_WRAPPER in test commit | commitdiff | tree
2019-12-09 Eddie Hung-unwrap to create $lut not SB_LUT4 for opt_lut commit | commitdiff | tree
2019-12-09 Eddie HungSensitive to direct inst of $__ICE40_CARRY_WRAPPER... commit | commitdiff | tree
2019-12-09 Eddie Hungice40_wrapcarry to really preserve attributes via ... commit | commitdiff | tree
2019-12-07 David Shahecp5: Add support for mapping PRLD FFs commit | commitdiff | tree
2019-12-07 Eddie HungMerge pull request #1555 from antmicro/fix-macc-xilinx... commit | commitdiff | tree
2019-12-07 Eddie HungDrop keep=0 attributes on SB_CARRY commit | commitdiff | tree
2019-12-06 Jan Kowalewskitests: arch: xilinx: Change order of arguments in macc.sh commit | commitdiff | tree
2019-12-05 Clifford WolfMerge pull request #1551 from whitequark/manual-cell... commit | commitdiff | tree
2019-12-05 Eddie HungMerge SB_CARRY+SB_LUT4's attributes when creating ... commit | commitdiff | tree
2019-12-05 Eddie HungAdd WIP test for unwrapping $__ICE40_CARRY_WRAPPER commit | commitdiff | tree
2019-12-04 whitequarkkernel: require \B_SIGNED=0 on $shl, $sshl, $shr, ... commit | commitdiff | tree
2019-12-04 whitequarkmanual: document behavior of many comb cells more preci... commit | commitdiff | tree
2019-12-04 Marcin Kościelnickixilinx: Add tristate buffer mapping. (#1528) commit | commitdiff | tree
2019-12-04 Marcin Kościelnickiiopadmap: Refactor and fix tristate buffer mapping... commit | commitdiff | tree
2019-12-04 Marcin Kościelnickixilinx: Add models for LUTRAM cells. (#1537) commit | commitdiff | tree
2019-12-03 Eddie HungCheck SB_CARRY name also preserved commit | commitdiff | tree
2019-12-03 Eddie Hung$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for... commit | commitdiff | tree
2019-12-03 Eddie Hungice40_opt to ignore (* keep *) -ed cells commit | commitdiff | tree
2019-12-03 Eddie Hungice40_wrapcarry to preserve SB_CARRY's attributes commit | commitdiff | tree
2019-12-03 Eddie HungAdd testcase commit | commitdiff | tree
2019-12-03 Clifford WolfMerge pull request #1524 from pepijndevos/gowindffinit commit | commitdiff | tree
2019-12-03 Pepijn de Vosupdate test commit | commitdiff | tree
2019-12-03 Pepijn de VosUse -match-init to not synth contradicting init values commit | commitdiff | tree
2019-12-02 David ShahMerge pull request #1542 from YosysHQ/dave/abc9-loop-fix commit | commitdiff | tree
2019-12-02 Clifford WolfMerge pull request #1539 from YosysHQ/mwk/ilang-bounds... commit | commitdiff | tree
2019-12-01 David Shahabc9: Fix breaking of SCCs commit | commitdiff | tree
2019-11-29 Miodrag MilanovićMerge pull request #1540 from YosysHQ/mwk/xilinx-bufpll commit | commitdiff | tree
2019-11-29 Marcin Kościelnickixilinx: Add missing blackbox cell for BUFPLL. commit | commitdiff | tree
2019-11-28 Eddie HungRevert "Fold loop" commit | commitdiff | tree
2019-11-27 Marcin Kościelnickiread_ilang: do bounds checking on bit indices commit | commitdiff | tree
2019-11-27 Diego HAdjusting Vivado's BRAM min bits threshold for RAMB18E1 commit | commitdiff | tree
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