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yosys.git
2014-02-21
Clifford Wolf
Added workaround for vhdl-style edge triggers from...
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2014-02-21
Clifford Wolf
Added vhdl2verilog
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2014-02-21
Clifford Wolf
Progress in presentation
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2014-02-21
Clifford Wolf
Better handling of nameDef and nameRef in edif backend
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2014-02-21
Clifford Wolf
Fixed instantiating multi-bit ports in edif backend
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2014-02-21
Clifford Wolf
Use private namespace in mem_simple_4x1_map
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2014-02-21
Clifford Wolf
Added tests/techmap/mem_simple_4x1
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2014-02-21
Clifford Wolf
Renamed "write_blif -subckt" to "write_blif -icells...
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2014-02-21
Clifford Wolf
Progress in presentation
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2014-02-20
Clifford Wolf
Progress in presentation
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2014-02-20
Clifford Wolf
Added _TECHMAP_REPLACE_ feature to techmap
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2014-02-20
Clifford Wolf
Added "extract -ignore_parameters" and "extract -ignore...
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2014-02-20
Clifford Wolf
Added "extract -map %<design_name>"
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2014-02-20
Clifford Wolf
Added "design -push" and "design -pop"
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2014-02-20
Clifford Wolf
Progress in presentation
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2014-02-20
Clifford Wolf
Added connwrappers command
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2014-02-20
Clifford Wolf
Cleanups in handling of read_verilog -defer and -icells
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2014-02-20
Clifford Wolf
Progress in presentation
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2014-02-19
Clifford Wolf
Added vcd2txt.pl and txt2tikztiming.py (tests/tools...
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2014-02-18
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-18
Clifford Wolf
Progress in presentation
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2014-02-18
Clifford Wolf
Added techmap support for _TECHMAP_CONNMAP_*_
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2014-02-18
Clifford Wolf
Added "sat -dump_cnf"
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2014-02-18
Clifford Wolf
Coding style corrections in SatHelper::dump_model_to_vcd()
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2014-02-18
Clifford Wolf
Improved non-verbose ezSAT::printDIMACS() format
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2014-02-18
Clifford Wolf
Added "sat -initsteps"
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2014-02-17
Clifford Wolf
Added Verilog support for "`default_nettype none"
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2014-02-17
Clifford Wolf
Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd"...
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2014-02-17
Andrew Zonenberg
Added "-dump_fail_to_vcd" argument to SAT solver
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2014-02-17
Clifford Wolf
Progress in presentation
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2014-02-17
Clifford Wolf
Better preserve wires when flattening (in comparison...
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2014-02-16
Clifford Wolf
Progress in presentation
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2014-02-16
Clifford Wolf
Added some additional checks to techmap
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2014-02-16
Clifford Wolf
Added CONSTMSK and CONSTVAL feature to techmap
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2014-02-16
Clifford Wolf
Fixed handling of "keep" attribute on wires in opt_clean
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2014-02-16
Clifford Wolf
Added a warning note about error reporting to read_veri...
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2014-02-16
Clifford Wolf
Progress in presentation
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2014-02-16
Clifford Wolf
Fixed use of selection in splitnets command
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2014-02-16
Clifford Wolf
Added recursion support to techmap
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2014-02-16
Clifford Wolf
Progress in presentation
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2014-02-16
Clifford Wolf
Progress in presentation
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2014-02-16
Clifford Wolf
Improved support for constant functions
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2014-02-15
Clifford Wolf
Now we are in Yoys 0.2.0+ development
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2014-02-15
Clifford Wolf
Tagging Yoys 0.2.0
yosys-0.2.0
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2014-02-15
Clifford Wolf
Added != support for relational select pattern
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2014-02-15
Clifford Wolf
Added iopadmap -bits
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2014-02-15
Clifford Wolf
Added ff and latch support to read_liberty
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2014-02-15
Clifford Wolf
Bugfix in expression parser of read_liberty
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2014-02-15
Clifford Wolf
Fixed dfflibmap for cell libraries with no set-reset-ff
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2014-02-15
Clifford Wolf
Correctly convert constants to RTLIL (fixed undef handling)
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2014-02-15
Clifford Wolf
Added frontend (-f) option to autotest.sh
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2014-02-15
Clifford Wolf
Fixed opt_const handling of double invert with non...
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2014-02-15
Clifford Wolf
Added liberty frontend
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2014-02-14
Clifford Wolf
Be more conservative with new const-function code
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2014-02-14
Clifford Wolf
Added support for FOR loops in function calls in parameters
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2014-02-14
Clifford Wolf
Created basic support for function calls in parameter...
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2014-02-14
Clifford Wolf
Added abc -keepff option
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2014-02-13
Clifford Wolf
updated default ABC command strings
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2014-02-13
Clifford Wolf
Updated ABC
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2014-02-13
Clifford Wolf
Implemented read_verilog -defer
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2014-02-13
Clifford Wolf
Removed double blanks in ABC default command sequences
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2014-02-13
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-13
Clifford Wolf
Updated ABC and some related changes
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2014-02-12
Clifford Wolf
Merge pull request #26 from ahmedirfan1983/btor
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2014-02-12
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-12
Clifford Wolf
Added support for functions returning integer
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2014-02-12
Ahmed Irfan
modified btor synthesis script for correct use of splic...
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2014-02-12
Clifford Wolf
Disabled "abc -dff" in "make test" for now (waiting...
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2014-02-12
Clifford Wolf
Updated ABC to rev e97a6e1d59b9
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2014-02-11
Clifford Wolf
renamed ilang "scope error" to "ilang error"
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2014-02-11
Ahmed Irfan
disabling splice command in the script
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2014-02-11
Ahmed Irfan
register output corrected
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2014-02-11
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-02-11
Ahmed Irfan
added concat and slice cell translation
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2014-02-11
Clifford Wolf
More Makefile cleanups
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2014-02-11
Clifford Wolf
Improved "make manual" and "make clean"
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2014-02-09
Clifford Wolf
Improved ilang parser error messages
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2014-02-09
Clifford Wolf
fixed a bug in subcircuit library with cells that have...
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2014-02-09
Clifford Wolf
Various improvements in expose command (added -sep...
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2014-02-09
Clifford Wolf
Added delete {-input|-output|-port}
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2014-02-09
Clifford Wolf
Bugfix in delete command
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2014-02-08
Clifford Wolf
Added test cases for expose -evert-dff
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2014-02-08
Clifford Wolf
Fixed handling of async reset in expose -evert-dff
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2014-02-08
Clifford Wolf
Build fixes for log cmd
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2014-02-08
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-08
Clifford Wolf
Implemented expose -evert-dff
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2014-02-08
Clifford Wolf
Merge pull request #24 from hansiglaser/master
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2014-02-08
Johann Glaser
added "log" command
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2014-02-08
Clifford Wolf
Improved checking of internal cell conventions
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2014-02-08
Clifford Wolf
Fixed bug in collecting of RD_TRANSPARENT parameter...
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2014-02-08
Clifford Wolf
Added various new options to splice command
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2014-02-08
Clifford Wolf
Added %a select operator
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2014-02-08
Clifford Wolf
Moved some passes to other source directories
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2014-02-08
Clifford Wolf
Added support for "keep" attribute to abc pass
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2014-02-08
Clifford Wolf
Added opt -purge (frontend to opt_clean -purge)
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2014-02-08
Clifford Wolf
Only count non-trivial attributes when findinf master...
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2014-02-08
Clifford Wolf
Added checking for ABC modifications to Makefile and...
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2014-02-07
Clifford Wolf
Now also move net labes to the right position in splice cmd
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2014-02-07
Clifford Wolf
Improved detection of primary wire for a signal in...
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2014-02-07
Clifford Wolf
Added splice command
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