yosys.git
2013-11-25 Clifford WolfStarted implementing undef handling in satgen
2013-11-25 Clifford WolfRemoved undef feature from ezsat api
2013-11-24 Clifford WolfUsing simplemap mappers from techmap
2013-11-24 Clifford WolfAdded simplemap pass
2013-11-24 Clifford WolfRenamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 Clifford WolfAdded module->avail_parameters (for advanced techmap...
2013-11-24 Clifford WolfAdded techmap -D and -I options
2013-11-24 Clifford WolfAdded verilog frontend -ignore_redef option
2013-11-24 Clifford WolfAdded "techmap -share_map" option
2013-11-24 Clifford WolfEarly wire/reg/parameter width calculation in ast/simplify
2013-11-24 Clifford WolfUpdated TODOs
2013-11-24 Clifford WolfFixed xilinx/example_sim_counter test bench
2013-11-24 Clifford WolfAdded proper dumping of signed/unsigned parameters...
2013-11-24 Clifford WolfAdded support for signed parameters in ilang
2013-11-24 Clifford WolfRemoved now obsolete test cases
2013-11-24 Clifford WolfRemove auto_wire framework (smarter than the verilog...
2013-11-24 Clifford WolfImplemented correct handling of signed module parameters
2013-11-24 Clifford WolfAdded modelsim support to autotest
2013-11-24 Clifford WolfFixed "flatten" top-module detection: Only use on fully...
2013-11-24 Clifford WolfFixed "make install" dependencies
2013-11-24 Clifford WolfAdded "top" attribute to mark top module in hierarchy
2013-11-23 Clifford WolfUpdated command-reference-manual.tex
2013-11-23 Clifford WolfAppNote 010 typo fixes and corrections
2013-11-23 Clifford WolfAppNote 010 progress
2013-11-23 Clifford WolfImproved handling of techmap special wires
2013-11-23 Clifford WolfImproved handling of initialized registers
2013-11-23 Clifford WolfAdded more generic _TECHMAP_ wire mechanism to techmap...
2013-11-23 Clifford WolfMaking prograss on Appnote 010
2013-11-22 Clifford WolfProgress on AppNote 010
2013-11-22 Clifford WolfStarted to write on AppNote 010: Verilog to BLIF
2013-11-22 Clifford WolfUpdated command-reference-manual.tex
2013-11-22 Clifford WolfRenamed "placeholder" to "blackbox"
2013-11-22 Clifford WolfSome driver changes/fixes
2013-11-22 Clifford WolfFixed O(n^2) performance bug in verilog preprocessor
2013-11-22 Clifford WolfAdded more performance measurement infrastructure
2013-11-22 Clifford WolfEnable {* .. *} feature per default (removes dependency...
2013-11-22 Clifford WolfMassive performance improvement from refactoring RTLIL...
2013-11-22 Clifford WolfAdded SigBit struct and refactored RTLIL::SigSpec:...
2013-11-22 Clifford WolfImproved make rules for profiling and debugging
2013-11-21 Clifford WolfUpdated abc
2013-11-21 Clifford WolfImplemented $_DFFSR_ expression generator in verilog...
2013-11-21 Clifford WolfFixed async proc detection in mem2reg
2013-11-21 Clifford WolfMajor improvements in mem2reg and added "init" sync...
2013-11-21 Clifford WolfFixed a bug in "add -global_input"
2013-11-20 Clifford WolfAdded "proc_arst -global_arst" feature
2013-11-20 Clifford WolfFixed ilang parser: memory width
2013-11-20 Clifford WolfAdded "add" command (only wires for now)
2013-11-20 Clifford WolfAnother name resolution bugfix for generate blocks
2013-11-20 Clifford WolfImplemented indexed part selects
2013-11-20 Clifford WolfDo not allow memory bit select on the left side of...
2013-11-20 Clifford WolfAdded "synthesis" in (synopsys|synthesis) comment support
2013-11-20 Clifford WolfFixed name resolution of local tasks and functions...
2013-11-20 Clifford WolfImplemented part/bit select on memory read
2013-11-20 Clifford WolfUpdated TODOs in README file
2013-11-20 Clifford WolfAdded init= attribute for fpga-style reset values
2013-11-19 Clifford WolfAdded "make config-sudo"
2013-11-19 Clifford WolfInstall simlib in datdir
2013-11-19 Clifford WolfLarge improvements in yosys-config
2013-11-19 Clifford WolfFixed parsing of module arguments when one type is...
2013-11-19 Clifford WolfRenamed temp module generated by "abc" pass from "logic...
2013-11-18 Clifford WolfAdded additional mem2reg testcase
2013-11-18 Clifford WolfFixed two bugs in mem2reg functionality in AST frontend
2013-11-18 Clifford WolfAdded dumping of attributes in AST frontend
2013-11-18 Clifford WolfFixed parsing of default cases when not last case
2013-11-18 Clifford WolfFixed mem2reg for reg usage outside always block
2013-11-18 Clifford WolfAdded commented-out osu025 maping commands to cmos...
2013-11-17 Clifford WolfAdded -v<level> option and some minor driver cleanups
2013-11-16 Clifford WolfRenamed ABCHGPULL to ABCPULL in Makefile
2013-11-13 Clifford WolfImproved building of yosys-abc
2013-11-13 Clifford WolfFixed abc pass blif parser for constant bits
2013-11-13 Clifford WolfFixed parsing of "parameter integer"
2013-11-10 Clifford WolfCleanups and bugfixes in response to new internal cell...
2013-11-10 Clifford WolfAdded information on all internal cell types to interna...
2013-11-10 Clifford WolfCall internal checker more often
2013-11-09 Clifford WolfImproved user-friendliness of "sat" and "eval" expressi...
2013-11-09 Clifford WolfSilenced a gcc warning in spice backend
2013-11-09 Clifford WolfAdded verification of SAT model to "eval -vloghammer_re...
2013-11-08 Clifford WolfMore undef-propagation related fixes
2013-11-08 Clifford WolfFixed handling of different signedness in power operands
2013-11-08 Clifford WolfFixed keep attribute on wires in opt_clean
2013-11-08 Clifford WolfImplemented const folding of ternary op with undef...
2013-11-08 Clifford WolfRemoved debug log from const_pow()
2013-11-07 Clifford WolfFixed handling of power operator
2013-11-07 Clifford WolfFixed more extend vs. extend_u0 issues
2013-11-07 Clifford WolfDisabled const folding of ternary op when select is...
2013-11-07 Clifford WolfRenamed extend_un0() to extend_u0() and use it in genrtlil
2013-11-07 Clifford WolfFixed type of sign extension in opt_const $eq/$ne handling
2013-11-07 Clifford WolfFixed sign handling in constants
2013-11-07 Clifford WolfFixed const folding in corner cases with parameters
2013-11-07 Clifford WolfRemoved done or obsolete TODO items
2013-11-07 Clifford WolfFixed width detection for replicate operator
2013-11-07 Clifford WolfFixed $eq/$ne bitwise optimization in opt_const
2013-11-07 Clifford WolfFixed at_zero evaluation of dynamic ranges
2013-11-07 Clifford WolfVarious fixes for correct parameter support
2013-11-07 Clifford WolfFixed the fix for propagation of width hints for $signe...
2013-11-06 Clifford WolfFixed techmap of $reduce_xnor with multi-bit outputs
2013-11-06 Clifford WolfFixed techmap of $gt and $ge with multi-bit outputs
2013-11-06 Clifford WolfAdded handling of unconnected/unspecified signals to...
2013-11-06 Clifford WolfFixed propagation of width hints for $signed() and...
2013-11-06 Clifford WolfImproved undef handling in == and != for ConstEval
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