yosys.git
2019-11-27 Eddie HungRevert "submod to bitty rather bussy, for bussy wires...
2019-11-27 Eddie HungPromote output wires in sigmap so that can be detected
2019-11-27 Eddie HungFix wire width
2019-11-27 Eddie HungFix submod -hidden
2019-11-27 Eddie HungAdd -hidden option to submod
2019-11-26 Eddie HungUpdate docs with bullet points
2019-11-26 Eddie HungMove \init from source wire to submod if output port
2019-11-26 Eddie HungAdd testcase where \init is copied
2019-11-23 Eddie HungRemove redundant flatten
2019-11-23 Eddie Hungsubmod to bitty rather bussy, for bussy wires used...
2019-11-23 Eddie HungStray dump
2019-11-23 Eddie HungConstant driven signals are also an input to submodules
2019-11-23 Eddie HungAdd another test with constant driver
2019-11-23 Eddie HungOops
2019-11-23 Eddie HungCleanup spacing
2019-11-23 Eddie Hungsigmap(wire) should inherit port_output status of POs
2019-11-23 Eddie HungAdd testcase
2019-11-22 Clifford WolfMerge pull request #1517 from YosysHQ/clifford/optmem
2019-11-22 Clifford WolfMerge pull request #1515 from YosysHQ/clifford/svastuff
2019-11-22 Clifford WolfAdd "opt_mem" pass
2019-11-22 Clifford WolfAdd Verific support for SVA nexttime properties
2019-11-22 Clifford WolfImprove handling of verific primitives in "verific...
2019-11-22 Clifford WolfAdd Verific SVA support for "always" properties
2019-11-22 Clifford WolfMerge pull request #1511 from YosysHQ/dave/always
2019-11-22 Marcin Kościelnickigowin: Remove show command from tests.
2019-11-22 Marcin Kościelnickigowin: Add missing .gitignore entries
2019-11-22 David ShahUpdate CHANGELOG and README
2019-11-21 David Shahsv: Add tests for SV always types
2019-11-21 David Shahproc_dlatch: Add error handling for incorrect always_...
2019-11-21 David Shahsv: Correct parsing of always_comb, always_ff and alway...
2019-11-20 Clifford WolfMerge pull request #1507 from YosysHQ/clifford/verificfixes
2019-11-20 Clifford WolfCorrectly treat empty modules as blackboxes in Verific
2019-11-20 Clifford WolfDo not rename VHDL entities to "entity(impl)" when...
2019-11-19 Clifford WolfMerge pull request #1449 from pepijndevos/gowin
2019-11-19 Pepijn de VosRemove dff init altogether
2019-11-19 Marcin KościelnickiFix #1462, #1480.
2019-11-19 Marcin Kościelnickixilinx: Add simulation models for MULT18X18* and DSP48A*.
2019-11-18 Pepijn de Vosadd help for nowidelut and abc9 options
2019-11-18 Clifford WolfMerge pull request #1497 from YosysHQ/mwk/extract-fa-fix
2019-11-18 whitequarkMerge pull request #1494 from whitequark/write_verilog...
2019-11-18 Marcin KościelnickiFix #1496.
2019-11-18 whitequarkwrite_verilog: add -extmem option, to write split memor...
2019-11-17 Clifford WolfMerge pull request #1492 from YosysHQ/dave/wreduce...
2019-11-16 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-15 David Shahecp5: Use new autoname pass for better cell/net names
2019-11-14 David Shahwreduce: Don't trim zeros or sext when not matching...
2019-11-14 Clifford WolfMerge pull request #1490 from YosysHQ/clifford/autoname
2019-11-14 Clifford WolfMerge pull request #1444 from btut/feature/python_wrapp...
2019-11-14 Clifford WolfMerge pull request #1465 from YosysHQ/dave/ice40_timing_sim
2019-11-14 Clifford WolfMerge branch 'makaimann-label-bads-btor'
2019-11-14 Clifford WolfUse cell name for btor bad state props when it is a...
2019-11-14 Clifford WolfMerge branch 'label-bads-btor' of https://github.com...
2019-11-13 Clifford WolfAdd "autoname" pass and use it in "synth_ice40"
2019-11-13 whitequarkMerge pull request #1488 from whitequark/flowmap-fixes
2019-11-13 Clifford WolfMerge pull request #1486 from YosysHQ/clifford/fsmdetectfix
2019-11-12 Clifford WolfUpdate fsm_detect bugfix
2019-11-12 Clifford WolfBugfix in fsm_detect
2019-11-12 Clifford WolfMerge pull request #1484 from YosysHQ/clifford/cmp2luteqne
2019-11-12 Makai MannAdd an info string symbol for bad states in btor backend
2019-11-12 whitequarkflowmap: when doing mincut, ensure source is always...
2019-11-11 whitequarkflowmap: don't break if that creates a k+2 (and larger...
2019-11-11 Pepijn de Vosfix fsm test with proper clock enable polarity
2019-11-11 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-11 Miodrag MilanovicFixed tests
2019-11-11 Clifford WolfDo not map $eq and $ne in cmp2lut, only proper arithmet...
2019-11-10 Clifford WolfMerge pull request #1470 from YosysHQ/clifford/subpassdoc
2019-11-07 Clifford WolfAdd check for valid macro names in macro definitions
2019-11-06 Pepijn de Vosfix wide luts
2019-11-06 Marcin Kościelnickisynth_xilinx: Merge blackbox primitive libraries.
2019-11-04 Clifford WolfFix write_aiger bug added in 524af21
2019-10-31 Clifford WolfAdd CodingReadme section on script passes
2019-10-30 Pepijn de Vosdon't cound exact luts in big muxes; futile and fragile
2019-10-28 Pepijn de Vosadd IOBUF
2019-10-28 Pepijn de Vosadd tristate buffer and test
2019-10-28 Pepijn de Vosdo not use wide luts in testcase
2019-10-28 Pepijn de Vosactually run the gowin tests
2019-10-28 Pepijn de VosMore formatting
2019-10-28 Pepijn de Vosreally really fix formatting maybe
2019-10-28 Pepijn de Vosundo formatting fuckup
2019-10-28 Pepijn de Vosadd wide luts
2019-10-28 Pepijn de Vosadd 32-bit BRAM and byte-enables
2019-10-27 Clifford WolfMerge pull request #1393 from whitequark/write_verilog...
2019-10-24 Pepijn de VosALU sim tweaks
2019-10-24 Clifford WolfImprove naming scheme for (VHDL) modules imported from...
2019-10-24 David ShahMerge pull request #1455 from YosysHQ/dave/ultrascaleplus
2019-10-24 Clifford WolfAdd "verific -L"
2019-10-23 David Shahice40: Add post-pnr ICESTORM_RAM model and fix FFs
2019-10-23 David Shahice40: Support for post-pnr timing simulation
2019-10-23 David Shahxilinx: Add URAM288 mapping for xcup
2019-10-23 David Shahxilinx: Add support for UltraScale[+] BRAM mapping
2019-10-22 Clifford WolfBugfix in smtio vcd handling of $-identifiers
2019-10-22 Marcin Kościelnickixilinx: Support multiplier mapping for all families.
2019-10-22 Clifford WolfMerge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
2019-10-21 Pepijn de VosAdd some tests
2019-10-21 Pepijn de Vosadd a few more missing dff
2019-10-21 Clifford WolfAdd "verilog_defines -list" and "verilog_defines -reset"
2019-10-21 Clifford WolfFix handling of "restrict" in Verific front-end
2019-10-21 Pepijn de Vosadd negedge DFF
2019-10-21 Pepijn de Vosuse ADDSUB ALU mode to remove inverters
2019-10-21 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
next