yosys.git
2017-05-15 Clifford WolfImprove simplec back-end
2017-05-14 Clifford WolfImprove simplec back-end
2017-05-13 Clifford WolfImprove simplec back-end
2017-05-12 Clifford WolfImprove simplec back-end
2017-05-12 Clifford WolfAdded support for more gate types to simplec back-end
2017-05-12 Clifford WolfAdd first draft of simple C back-end
2017-05-11 Clifford WolfUpdate ABC to hg rev e79576e10d72
2017-05-08 Clifford WolfFix boolector support in yosys-smtbmc
2017-04-30 Clifford WolfAdd support for localparam in module header
2017-04-28 Clifford WolfFix equiv_simple, old behavior now available with ...
2017-04-26 Clifford WolfAdd support for `resetall compiler directive
2017-04-12 Clifford WolfReplace CRLF line endings with LF in de2i.qsf (quartus...
2017-04-12 Larry DoolittleSquelch trailing whitespace
2017-04-07 Clifford WolfAdd MAX10 and Cyclone IV items to CHANGELOG
2017-04-07 Clifford WolfMerge pull request #337 from dh73/master
2017-04-06 dh73Add initial support for both MAX10 and Cyclone IV ...
2017-04-05 Clifford WolfAdd ConstEval defaultval feature
2017-04-05 Clifford WolfFix gcc compiler warning
2017-03-28 Clifford WolfAdd front-end detection for *.tcl files
2017-03-27 Clifford WolfAdd minisat 00_PATCH_typofixes.patch
2017-03-27 Clifford WolfRemove use of <fpu_control.h> in minisat
2017-03-20 Clifford WolfAdd "write_smt2 -stdt" mode
2017-03-19 Clifford WolfAdd generation of logic cells to EDIF back-end runtest.py
2017-03-19 Clifford WolfFix EDIF: portRef member 0 is always the MSB bit
2017-03-18 Clifford WolfAdd simple EDIF test case generator and checker
2017-03-14 Clifford WolfFix verilog pre-processor for multi-level relative...
2017-03-04 Clifford WolfImprove smt2 encodings of assert/assume/cover, better...
2017-03-02 Clifford WolfAdd write_aiger $anyseq support
2017-03-01 Clifford WolfAllow $anyconst, etc. in non-formal SV mode
2017-02-28 Clifford WolfDisable opt_merge for $anyseq and $anyconst
2017-02-28 Clifford WolfUse hex addresses in smtbmc vcd mem traces
2017-02-27 Clifford WolfAdd "chformal -assert2assume" and friends
2017-02-27 Clifford WolfAdd "chformal" pass
2017-02-26 Clifford WolfAdd smtbmc support for memory vcd dumping
2017-02-26 Clifford WolfFix extra newline bug in write_smt2
2017-02-26 Clifford WolfFix bug in smtio unroll code
2017-02-26 Clifford WolfFix assert checking in "yosys-smtbmc -c --append"
2017-02-26 Clifford WolfImprove (and fix for stbv mode) SMT2 memory API
2017-02-25 Clifford WolfAdd support for "yosys-smtbmc -c --append"
2017-02-25 Clifford WolfUpdate ABC to hg rev 3a95bfa55df7
2017-02-25 Clifford WolfMerge branch 'klammerj-master'
2017-02-25 Clifford WolfImprove "write_edif" help message
2017-02-25 Clifford WolfMove EdifNames out of double-private namespace
2017-02-25 Clifford WolfClean up edif code, swap bit indexing of "upto" ports
2017-02-25 Clifford WolfMerge branch 'master' of https://github.com/klammerj...
2017-02-25 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-02-25 Clifford WolfAdd $live and $fair support to AIGER back-end.
2017-02-25 Clifford WolfAdd $live and $fair cell types, add support for s_event...
2017-02-24 Clifford WolfMerge pull request #322 from azonenberg/master
2017-02-24 Clifford WolfAdd "write_smt2 -stbv"
2017-02-24 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-24 Clifford WolfAdd SMT2 statebv mode (inactive for now)
2017-02-24 Johann KlammerDid as you requested, /but/...
2017-02-24 Clifford WolfMerge pull request #320 from joshhead/uninstall-binpath-fix
2017-02-24 Josh HeadapohlAdd missing slashes in paths for make uninstall
2017-02-23 Johann Klammeradd options for edif flavors
2017-02-23 Clifford WolfAdd support for SystemVerilog unique, unique0, and...
2017-02-23 Clifford WolfPreserve string parameters
2017-02-23 Clifford WolfFix mingw compile issue (2nd attempt)
2017-02-23 Clifford WolfFix mingw compile issue (maybe.. I can't test it)
2017-02-23 Clifford WolfAdded SystemVerilog support for ++ and --
2017-02-22 Clifford WolfUpdate ABC to hg rev 8da4dc435b9f
2017-02-19 Clifford WolfAdd "yosys-smtbmc -S <opt>"
2017-02-16 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-16 Clifford WolfCopy attributes to _TECHMAP_REPLACE_ cells
2017-02-16 Clifford WolfFix eval implementation of $_NOR_
2017-02-14 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-14 Clifford WolfFix incorrect "incompatible re-declaration of wire...
2017-02-14 Clifford WolfAdd warning about x/z bits left unconnected in EDIF...
2017-02-14 Clifford WolfFix double-call of log_pop() in synth_greenpak4
2017-02-14 Clifford WolfMerge pull request #313 from azidar/bugfix-assign-wmask
2017-02-13 Adam IzraelevitzMore progress on Firrtl backend.
2017-02-13 Clifford WolfDo not fix port widths on any blackbox instances
2017-02-13 Clifford WolfFix techmap for inout ports connected to inout ports
2017-02-12 Clifford WolfDo not eagerly fix port widths on parameterized cells
2017-02-12 Clifford WolfAdd "yosys -w" for suppressing warnings
2017-02-11 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-11 Clifford WolfAdd support for verific mem initialization
2017-02-11 Clifford WolfFix another stupid bug in the same line
2017-02-11 Clifford WolfAdd verific support for initialized variables
2017-02-11 Clifford WolfImprove handling of Verific warnings and error messages
2017-02-11 Clifford WolfFix extremely stupid typo
2017-02-11 Clifford WolfAdd log_wire() API
2017-02-11 Clifford WolfFixed some "used uninitialized" warnings in opt_expr
2017-02-11 Clifford WolfEvaluate all the $(shell ...) stuff for CXXFLAGS et...
2017-02-11 Clifford WolfMerge branch 'stv0g-master'
2017-02-11 Clifford WolfMake MacOS Makefile stuff more compact
2017-02-11 Clifford WolfMerge branch 'master' of https://github.com/stv0g/yosys...
2017-02-11 Clifford WolfAdd optimization of (a && 1'b1) and (a || 1'b0)
2017-02-11 Clifford WolfMerge pull request #308 from C-Elegans/opt_compare_fix_pr
2017-02-10 C-ElegansFix issue #306, "Bug in opt -full"
2017-02-10 Steffen VogelUse pkg-config for linking tcl-tk
2017-02-10 Steffen VogelDont mix Homebrew and MacPorts build options
2017-02-09 Steffen VogelRemove space after backslash
2017-02-09 Steffen VogelApplied fixes from @joshhead (thanks for your effors!)
2017-02-09 Clifford WolfFix handling of init attributes with strange width
2017-02-09 Clifford WolfAdd checker support to verilog front-end
2017-02-09 Clifford WolfAdd "rand" and "rand const" verific support
2017-02-09 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-08 Clifford WolfAdd SV "rand" and "const rand" support
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