yosys.git
2019-12-18 Marcin Kościelnickixilinx: Add xilinx_dffopt pass (#1557)
2019-12-18 Marcin Kościelnickixilinx: Improve flip-flop handling.
2019-12-18 Clifford WolfSend people to symbioticeda.com instead of verific.com
2019-12-18 N. Engelhardtuse extra_args
2019-12-18 Eddie HungRemove &verify -s
2019-12-18 Eddie HungBump ABC for upstream fix
2019-12-18 Eddie HungUse pool<> instead of std::set<> to preserver ordering
2019-12-17 Eddie Hungaiger frontend to user shorter, $-prefixed, names
2019-12-17 Eddie HungCleanup xaiger, remove unnecessary complexity with...
2019-12-17 Eddie Hungread_xaiger to cope with optional '\n' after 'c'
2019-12-17 Clifford WolfFix sim for assignments with lhs<rhs size, fixes #1565
2019-12-17 Eddie HungCleanup
2019-12-17 Eddie HungDo not sigmap
2019-12-17 Eddie HungRevert "Use sigmap signal"
2019-12-17 Eddie HungMerge pull request #1574 from YosysHQ/eddie/xilinx_lutram
2019-12-17 Eddie HungMerge pull request #1521 from dh73/diego/memattr
2019-12-17 Eddie Hungabc9 needs a clean afterwards
2019-12-17 Eddie HungEnforce non-existence
2019-12-17 Eddie HungPut $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop
2019-12-17 Eddie HungUse sigmap signal
2019-12-16 Eddie HungUpdate doc
2019-12-16 Eddie HungSkip $inout transformation if not a PI
2019-12-16 Eddie HungRevert "write_xaiger: use sigmap bits more consistently"
2019-12-16 Eddie HungAdd another test
2019-12-16 Eddie HungMore sloppiness, thanks @dh73 for spotting
2019-12-16 Eddie HungAccidentally commented out tests
2019-12-16 Eddie HungAdd unconditional match blocks for force RAM
2019-12-16 Eddie HungOops
2019-12-16 Eddie HungMerge blockram tests
2019-12-16 Eddie HungUpdate xc7/xcu bram rules
2019-12-16 Eddie HungImplement 'attributes' grammar
2019-12-16 Eddie HungMerge branch 'diego/memattr' of https://github.com...
2019-12-16 Eddie HungMerge branch 'eddie/xilinx_lutram' of github.com:YosysH...
2019-12-16 Eddie HungPopulate DID/DOD even if unused
2019-12-16 Eddie HungRename *RAM{32,64}M rules to RAM{32X2,64X1}Q
2019-12-16 Eddie Hungwrite_xaiger: use sigmap bits more consistently
2019-12-16 Diego HFixing compiler warning/issues. Moving test script...
2019-12-16 N. Engelhardtadd assert option to scratchpad command
2019-12-16 Diego HRemoving fixed attribute value to !ramstyle rules
2019-12-16 Diego HMerging attribute rules into a single match block;...
2019-12-16 Eddie HungMerge pull request #1575 from rodrigomelo9/master
2019-12-16 Eddie HungMerge pull request #1577 from gromero/for-yosys
2019-12-16 Eddie HungMerge pull request #1578 from noopwafel/eqneq-debug
2019-12-15 Alyssa MilburnFix opt_expr.eqneq.cmpzero debug print
2019-12-14 Eddie HungName inputs/outputs of aiger 'i%d' and 'o%d'
2019-12-13 Diego HRefactoring memory attribute matching based on IEEE...
2019-12-13 Eddie HungMerge pull request #1533 from dh73/bram_xilinx
2019-12-13 Eddie HungDisable RAM16X1D test
2019-12-13 Eddie HungDisable RAM16X1D match rule; carry-over from LUT4 arches
2019-12-13 Eddie HungRAM64M8 to also have [5:0] for address
2019-12-13 Diego HRenaming BRAM memory tests for the sake of uniformity
2019-12-13 Rodrigo Alejandro... Fixed some missing "verilog_" in documentation
2019-12-13 N. Engelhardtadd periods and newlines to help message
2019-12-13 Eddie HungRemove extraneous synth_xilinx call
2019-12-13 Eddie HungAdd tests for these new models
2019-12-13 Eddie HungAdd RAM32X6SDP and RAM64X3SDP modes
2019-12-13 Eddie HungFix RAM64M model to have 6 bit address bus
2019-12-13 Eddie HungAdd #1460 testcase
2019-12-13 Eddie HungAdd memory rules for RAM16X1D, RAM32M, RAM64M
2019-12-13 Eddie HungRename memory tests to lutram, add more xilinx tests
2019-12-12 Diego HFixing citation in xc7_xcu_brams.txt file. Fixing RAMB3...
2019-12-12 Eddie HungRemove 'clkpart' entry in CHANGELOG
2019-12-12 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-12 Eddie Hungabc9_map.v: fix Xilinx LUTRAM
2019-12-12 Eddie Hungabc9_map.v: fix Xilinx LUTRAM
2019-12-12 Diego HAdding a note (TODO) in the memory_params.ys check...
2019-12-12 N. Engelhardtadd test and make help message more verbose
2019-12-12 Diego HUpdating RAMB36E1 thresholds. Adding test for both...
2019-12-12 Diego HMerge https://github.com/YosysHQ/yosys into bram_xilinx
2019-12-12 Eddie HungMake SV2017 compliant courtesy of @wsnyder
2019-12-12 N. Engelhardtadd a command to read/modify scratchpad contents
2019-12-12 Eddie HungStray log_dump
2019-12-12 Eddie HungPreserve size of $genval$-s in for loops
2019-12-12 Eddie HungAdd testcase
2019-12-12 Eddie HungUpdate README.md :: abc_ -> abc9_
2019-12-11 Eddie HungFix bitwidth mismatch; suppresses iverilog warning
2019-12-11 Gustavo Romeromanual: Fix text in Abstract section
2019-12-11 David ShahMerge pull request #1564 from ZirconiumX/intel_housekeeping
2019-12-10 Dan Ravensloftsynth_intel: a10gx -> arria10gx
2019-12-10 Dan Ravensloftsynth_intel: cyclone10 -> cyclone10lp
2019-12-10 Eddie HungMerge pull request #1545 from YosysHQ/eddie/ice40_wrapc...
2019-12-09 Eddie HungFix comment
2019-12-09 Eddie Hungice40_opt to restore attributes/name when unwrapping
2019-12-09 Eddie Hungice40_wrapcarry -unwrap to preserve 'src' attribute
2019-12-09 Eddie Hungunmap $__ICE40_CARRY_WRAPPER in test
2019-12-09 Eddie Hung-unwrap to create $lut not SB_LUT4 for opt_lut
2019-12-09 Eddie HungSensitive to direct inst of $__ICE40_CARRY_WRAPPER...
2019-12-09 Eddie Hungice40_wrapcarry to really preserve attributes via ...
2019-12-07 David Shahecp5: Add support for mapping PRLD FFs
2019-12-07 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-07 Eddie HungMerge pull request #1555 from antmicro/fix-macc-xilinx...
2019-12-07 Eddie HungDrop keep=0 attributes on SB_CARRY
2019-12-07 Eddie HungStray newline
2019-12-07 Eddie Hungwrite_xaiger to inst each cell type once, do not call...
2019-12-07 Eddie Hungtechmap/aigmap of whiteboxes to occur before abc9 inste...
2019-12-07 Eddie HungCall abc9 with "&write -n", and parse_xaiger() to cope
2019-12-07 Eddie HungRemove creation of $abc9_control_wire
2019-12-07 Eddie HungDo not connect undriven POs to 1'bx
2019-12-07 Eddie HungFix abc9 re-integration, remove abc9_control_wire,...
2019-12-07 Eddie HungFix writing non-whole modules, including inouts and...
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