2019-12-18 |
Marcin Kościelnicki | xilinx: Add xilinx_dffopt pass (#1557) |
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2019-12-18 |
Marcin Kościelnicki | xilinx: Improve flip-flop handling. |
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2019-12-18 |
Clifford Wolf | Send people to symbioticeda.com instead of verific.com |
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2019-12-18 |
N. Engelhardt | use extra_args |
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2019-12-18 |
Eddie Hung | Remove &verify -s |
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2019-12-18 |
Eddie Hung | Bump ABC for upstream fix |
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2019-12-18 |
Eddie Hung | Use pool<> instead of std::set<> to preserver ordering |
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2019-12-17 |
Eddie Hung | aiger frontend to user shorter, $-prefixed, names |
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2019-12-17 |
Eddie Hung | Cleanup xaiger, remove unnecessary complexity with... |
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2019-12-17 |
Eddie Hung | read_xaiger to cope with optional '\n' after 'c' |
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2019-12-17 |
Clifford Wolf | Fix sim for assignments with lhs<rhs size, fixes #1565 |
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2019-12-17 |
Eddie Hung | Cleanup |
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2019-12-17 |
Eddie Hung | Do not sigmap |
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2019-12-17 |
Eddie Hung | Revert "Use sigmap signal" |
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2019-12-17 |
Eddie Hung | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram |
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2019-12-17 |
Eddie Hung | Merge pull request #1521 from dh73/diego/memattr |
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2019-12-17 |
Eddie Hung | abc9 needs a clean afterwards |
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2019-12-17 |
Eddie Hung | Enforce non-existence |
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2019-12-17 |
Eddie Hung | Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop |
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2019-12-17 |
Eddie Hung | Use sigmap signal |
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2019-12-16 |
Eddie Hung | Update doc |
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2019-12-16 |
Eddie Hung | Skip $inout transformation if not a PI |
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2019-12-16 |
Eddie Hung | Revert "write_xaiger: use sigmap bits more consistently" |
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2019-12-16 |
Eddie Hung | Add another test |
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2019-12-16 |
Eddie Hung | More sloppiness, thanks @dh73 for spotting |
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2019-12-16 |
Eddie Hung | Accidentally commented out tests |
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2019-12-16 |
Eddie Hung | Add unconditional match blocks for force RAM |
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2019-12-16 |
Eddie Hung | Oops |
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2019-12-16 |
Eddie Hung | Merge blockram tests |
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2019-12-16 |
Eddie Hung | Update xc7/xcu bram rules |
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2019-12-16 |
Eddie Hung | Implement 'attributes' grammar |
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2019-12-16 |
Eddie Hung | Merge branch 'diego/memattr' of https://github.com... |
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2019-12-16 |
Eddie Hung | Merge branch 'eddie/xilinx_lutram' of github.com:YosysH... |
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2019-12-16 |
Eddie Hung | Populate DID/DOD even if unused |
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2019-12-16 |
Eddie Hung | Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q |
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2019-12-16 |
Eddie Hung | write_xaiger: use sigmap bits more consistently |
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2019-12-16 |
Diego H | Fixing compiler warning/issues. Moving test script... |
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2019-12-16 |
N. Engelhardt | add assert option to scratchpad command |
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2019-12-16 |
Diego H | Removing fixed attribute value to !ramstyle rules |
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2019-12-16 |
Diego H | Merging attribute rules into a single match block;... |
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2019-12-16 |
Eddie Hung | Merge pull request #1575 from rodrigomelo9/master |
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2019-12-16 |
Eddie Hung | Merge pull request #1577 from gromero/for-yosys |
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2019-12-16 |
Eddie Hung | Merge pull request #1578 from noopwafel/eqneq-debug |
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2019-12-15 |
Alyssa Milburn | Fix opt_expr.eqneq.cmpzero debug print |
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2019-12-14 |
Eddie Hung | Name inputs/outputs of aiger 'i%d' and 'o%d' |
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2019-12-13 |
Diego H | Refactoring memory attribute matching based on IEEE... |
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2019-12-13 |
Eddie Hung | Merge pull request #1533 from dh73/bram_xilinx |
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2019-12-13 |
Eddie Hung | Disable RAM16X1D test |
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2019-12-13 |
Eddie Hung | Disable RAM16X1D match rule; carry-over from LUT4 arches |
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2019-12-13 |
Eddie Hung | RAM64M8 to also have [5:0] for address |
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2019-12-13 |
Diego H | Renaming BRAM memory tests for the sake of uniformity |
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2019-12-13 |
Rodrigo Alejandro... | Fixed some missing "verilog_" in documentation |
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2019-12-13 |
N. Engelhardt | add periods and newlines to help message |
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2019-12-13 |
Eddie Hung | Remove extraneous synth_xilinx call |
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2019-12-13 |
Eddie Hung | Add tests for these new models |
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2019-12-13 |
Eddie Hung | Add RAM32X6SDP and RAM64X3SDP modes |
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2019-12-13 |
Eddie Hung | Fix RAM64M model to have 6 bit address bus |
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2019-12-13 |
Eddie Hung | Add #1460 testcase |
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2019-12-13 |
Eddie Hung | Add memory rules for RAM16X1D, RAM32M, RAM64M |
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2019-12-13 |
Eddie Hung | Rename memory tests to lutram, add more xilinx tests |
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2019-12-12 |
Diego H | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB3... |
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2019-12-12 |
Eddie Hung | Remove 'clkpart' entry in CHANGELOG |
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2019-12-12 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig_dff |
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2019-12-12 |
Eddie Hung | abc9_map.v: fix Xilinx LUTRAM |
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2019-12-12 |
Eddie Hung | abc9_map.v: fix Xilinx LUTRAM |
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2019-12-12 |
Diego H | Adding a note (TODO) in the memory_params.ys check... |
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2019-12-12 |
N. Engelhardt | add test and make help message more verbose |
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2019-12-12 |
Diego H | Updating RAMB36E1 thresholds. Adding test for both... |
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2019-12-12 |
Diego H | Merge https://github.com/YosysHQ/yosys into bram_xilinx |
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2019-12-12 |
Eddie Hung | Make SV2017 compliant courtesy of @wsnyder |
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2019-12-12 |
N. Engelhardt | add a command to read/modify scratchpad contents |
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2019-12-12 |
Eddie Hung | Stray log_dump |
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2019-12-12 |
Eddie Hung | Preserve size of $genval$-s in for loops |
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2019-12-12 |
Eddie Hung | Add testcase |
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2019-12-12 |
Eddie Hung | Update README.md :: abc_ -> abc9_ |
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2019-12-11 |
Eddie Hung | Fix bitwidth mismatch; suppresses iverilog warning |
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2019-12-11 |
Gustavo Romero | manual: Fix text in Abstract section |
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2019-12-11 |
David Shah | Merge pull request #1564 from ZirconiumX/intel_housekeeping |
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2019-12-10 |
Dan Ravensloft | synth_intel: a10gx -> arria10gx |
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2019-12-10 |
Dan Ravensloft | synth_intel: cyclone10 -> cyclone10lp |
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2019-12-10 |
Eddie Hung | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapc... |
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2019-12-09 |
Eddie Hung | Fix comment |
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2019-12-09 |
Eddie Hung | ice40_opt to restore attributes/name when unwrapping |
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2019-12-09 |
Eddie Hung | ice40_wrapcarry -unwrap to preserve 'src' attribute |
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2019-12-09 |
Eddie Hung | unmap $__ICE40_CARRY_WRAPPER in test |
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2019-12-09 |
Eddie Hung | -unwrap to create $lut not SB_LUT4 for opt_lut |
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2019-12-09 |
Eddie Hung | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER... |
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2019-12-09 |
Eddie Hung | ice40_wrapcarry to really preserve attributes via ... |
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2019-12-07 |
David Shah | ecp5: Add support for mapping PRLD FFs |
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2019-12-07 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig_dff |
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2019-12-07 |
Eddie Hung | Merge pull request #1555 from antmicro/fix-macc-xilinx... |
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2019-12-07 |
Eddie Hung | Drop keep=0 attributes on SB_CARRY |
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2019-12-07 |
Eddie Hung | Stray newline |
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2019-12-07 |
Eddie Hung | write_xaiger to inst each cell type once, do not call... |
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2019-12-07 |
Eddie Hung | techmap/aigmap of whiteboxes to occur before abc9 inste... |
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2019-12-07 |
Eddie Hung | Call abc9 with "&write -n", and parse_xaiger() to cope |
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2019-12-07 |
Eddie Hung | Remove creation of $abc9_control_wire |
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2019-12-07 |
Eddie Hung | Do not connect undriven POs to 1'bx |
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2019-12-07 |
Eddie Hung | Fix abc9 re-integration, remove abc9_control_wire,... |
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2019-12-07 |
Eddie Hung | Fix writing non-whole modules, including inouts and... |
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