gem5.git
2013-07-11 Brad Beckmannruby: removed the very old double trigger hack stable_2013_10_14
2013-07-02 Nilay Vaishregressions: update a couple stats.txt
2013-07-02 Nilay Vaishregressions: update a couple of configs
2013-06-29 Nilay Vaishruby: append transition comment only when in opt/debug
2013-06-29 Nilay Vaishconfigs: rearrange the available options in Options.py
2013-06-29 Nilay Vaishruby: network: remove reconfiguration code
2013-06-29 Nilay Vaishruby: check for compatibility between mem size and...
2013-06-27 Andreas Hanssonstats: Update stats for monitor, cache and bus changes
2013-06-27 Prakash Ramrakhyanimem: Reorganize cache tags and make them a SimObject
2013-06-27 Andreas Hanssonmem: Remove the cache builder
2013-06-27 Andreas Hanssonconfig: Remove Clock parameter multiplication
2013-06-27 Akash Bagdiasim: Add the notion of clock domains to all ClockedObjects
2013-06-27 Andreas Hanssonconfig: Add a BaseSESystem builder for re-use in regres...
2013-06-27 Akash Bagdiaconfig: Rename clock option to Ruby clock
2013-06-27 Akash Bagdiaconfig: Add a system clock command-line option
2013-06-27 Akash Bagdiaconfig: Add a CPU clock command-line option
2013-06-27 Akash Bagdiaconfig: Remove redundant explicit setting of default...
2013-06-27 Andreas Hanssontests: Prune 00.gzip from the regressions
2013-06-27 Andreas Hanssonmem: Tidy up the bridge with const and additional checks
2013-06-27 Andreas Hanssonmem: Fix CommMonitor style and response check
2013-06-27 Andreas Hanssonmem: Align cache timing to clock edges
2013-06-27 Andreas Hanssoncpu: Consider instructions waiting for FU completion...
2013-06-27 Andreas Hanssonmem: Cycles converted to Ticks in atomic cache accesses
2013-06-27 Andreas Hanssonscons: Identify runs that fail and runs with stats...
2013-06-27 Andreas Hanssonbase: Fix address range granularity calculation
2013-06-27 Andreas Hanssonmem: Remove a redundant heap allocation for a snoop...
2013-06-27 Andreas Hanssonmem: Remove CoherentBus snoop port unused private member
2013-06-27 Sascha Bischoffstats: Remove printing of SparseHist total
2013-06-25 Nilay Vaishstats: updates due to changes to stat collection in...
2013-06-25 Nilay Vaishruby: moesi cmp directory: separate actions for externa...
2013-06-25 Nilay Vaishruby: mesi cmp directory: separate actions for external...
2013-06-25 Nilay Vaishruby: profiler: lots of inter-related changes
2013-06-24 Andreas Hanssonstats: Bump x86 stats
2013-06-24 Nilay Vaishruby: remove the three files related to profiling
2013-06-24 Joel Hestness... ruby: MessageBuffer: Remove unused m_size variable
2013-06-20 Lena Olsonruby: fix typo in MOESI_CMP_token protocol
2013-06-18 Lena Olsonruby: Fix prefetching for MESI_CMP_Directory
2013-06-18 Lena Olsonruby: fix slicc compiler to complain about duplicate...
2013-06-18 Lena Olsonruby: restrict Address to being a type and not a variab...
2013-06-18 Andreas Sandbergx86: Add support for maintaining the x87 tag word
2013-06-18 Andreas Sandbergx86: Fix loading of floating point constants
2013-06-18 Andreas Sandbergx86: Initialize the MXCSR register
2013-06-18 Andreas Sandbergx86: Make the boot state VMX compliant
2013-06-18 Andreas Sandbergx86: Make fprem like the fprem on a real x87
2013-06-18 Andreas Sandbergkvm: Use the address finalization code in the TLB
2013-06-18 Andreas Sandbergx86: Add helper functions to access rflags
2013-06-18 Andreas Sandbergx86: Fix the flag handling code in FABS and FCHS
2013-06-16 Nilay VaishAdded tag stable_2013_06_16 for changeset 07352f119e48
2013-06-13 Nilay Vaishconfig: Do not instantiate membus when using ruby
2013-06-11 Andreas Sandbergkvm: Add more VM stats
2013-06-11 Andreas Sandbergkvm: Separate host frequency from simulated CPU frequency
2013-06-11 Andreas Sandbergkvm: Don't handle IO and execute in the same tick
2013-06-11 Andreas Sandbergkvm: Maintain a local instruction counter and update...
2013-06-11 Andreas Sandbergx86: Fix bug when copying TSC on CPU handover
2013-06-11 Andreas Sandbergsim: Revert [34e3295b0e39] (sim: Fix early termination...
2013-06-11 Andreas Sandbergcpu: Add support for scheduling multiple inst/load...
2013-06-10 Nilay Vaishstats: updates due to changes to ruby
2013-06-09 Nilay Vaishruby: remove several unused variables in Profiler
2013-06-09 Nilay Vaishruby: remove periodic event from Profiler
2013-06-09 Nilay Vaishruby: stats: use gem5's stats for cache and memory...
2013-06-09 Nilay Vaishruby: remove undefined functions in Address class
2013-06-09 Nilay Vaishstats: allow printing vectors on a single line
2013-06-09 Nilay Vaishconfig: add atomic cpu to X86_MESI_CMP_directory build...
2013-06-08 Steve ReinhardtUpdating EIO regression reference outputs for new stats.
2013-06-04 Ali Saidiscons: ammend swig warning error to version 2.0.10...
2013-06-04 Andreas Sandbergdev: Clarify why updates are delayed when the MC14818...
2013-06-03 Andreas Sandbergarch: Create a method to finalize physical addresses
2013-06-03 Andreas Sandbergbase: Make the Python module loader PEP302 compliant
2013-06-03 Andreas Sandbergconfig: Add missing CPUs to --restore-with-cpu
2013-06-03 Andreas Sandbergkvm: Allow architectures to override the cycle accounti...
2013-06-03 Andreas Sandbergkvm: Add handling of EAGAIN when creating timers
2013-06-03 Andreas Sandbergsim: Add debug output when executing pseudo-instructions
2013-06-03 Andreas Sandbergkvm: Add a call to thread->startup() in startup()
2013-06-03 Andreas Sandbergdev: Add support for disabling ticking and the divider...
2013-06-03 Andreas Sandbergdev: Clean up MC146818 register (A & B) handling
2013-05-30 Andreas Hanssonstats: Update the stats to reflect bus and memory changes
2013-05-30 Andreas Hanssonmem: More descriptive DRAM config names
2013-05-30 Andreas Hanssonmem: Add bytes per activate DRAM controller stat
2013-05-30 Andreas Hanssonmem: Add static latency to the DRAM controller
2013-05-30 Andreas Hanssonmem: Spring cleaning of MSHR and MSHRQueue
2013-05-30 Andreas Hanssonmem: Fix MSHR print format
2013-05-30 Andreas Hanssoncpu: Prune the stale TraceCPU
2013-05-30 Sascha Bischoffcpu: Check that minimum TrafficGen period is less than...
2013-05-30 Sascha Bischoffcpu: Fix bug when reading in TrafficGen state transitions
2013-05-30 Andreas Hanssoncpu: Add request elasticity to the traffic generator
2013-05-30 Andreas Hanssoncpu: Block traffic generator when requests have to...
2013-05-30 Andreas Hanssoncpu: Move traffic generator sending out of generator...
2013-05-30 Andreas Hanssoncpu: Fold together the StateGraph and the TrafficGen
2013-05-30 Andreas Hanssonmem: Make returning snoop responses occupy response...
2013-05-30 Andreas Hanssonmem: Make the buses multi layered
2013-05-30 Andreas Hanssonmem: Separate the two snoop response cases in the bus
2013-05-30 Andreas Hanssonmem: Tidy up a few variables in the bus
2013-05-30 Uri Wienermem: Add basic stats to the buses
2013-05-30 Andreas Hanssonmem: Use unordered set in bus request tracking
2013-05-30 Andreas Hanssonmem: Check for waiting state in bus draining
2013-05-30 Andreas Hanssonmem: Add a LPDDR3-1600 configuration
2013-05-30 Andreas Hanssonmem: Adapt the LPDDR2 to match a single x32 channel
2013-05-30 Andreas Hanssonmem: Avoid explicitly zeroing the memory backing store
2013-05-30 Andreas Hanssonutil: Auto generate the packet proto definitions
2013-05-30 Andreas Hanssonbase: Avoid size limitation on protobuf coded streams
next