yosys.git
2019-07-19 Eddie HungAdd support for ice40 signed multipliers
2019-07-19 Eddie HungMerge branch 'xc7dsp' into ice40dsp
2019-07-19 Eddie HungFix typo in B
2019-07-19 Eddie HungMerge remote-tracking branch 'origin/eddie/signed_ice40...
2019-07-19 David Shahice40: Fix test_dsp_model.sh
2019-07-19 David Shahice40/cells_sim.v: Fix sign of J and K partial products
2019-07-19 Eddie HungUse sign_headroom instead
2019-07-19 David Shahice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
2019-07-19 Eddie HungAdd tests for all combinations of A and B signedness...
2019-07-19 Eddie HungDon't copy ref if exists already
2019-07-19 Eddie HungFix SB_MAC sim model -- do not sign extend internal...
2019-07-19 Eddie HungAdd params
2019-07-19 Eddie HungMerge remote-tracking branch 'origin/master' into ice40dsp
2019-07-19 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-07-18 Eddie HungDo not define `DSP_SIGNEDONLY macro if no exists
2019-07-18 Eddie HungMerge remote-tracking branch 'origin/master' into ice40dsp
2019-07-18 Eddie Hungice40_dsp to accept $__MUL16X16 too
2019-07-18 Eddie Hungsynth_ice40 to decompose into 16x16
2019-07-18 Eddie Hungmul2dsp to create cells that can be interchanged with...
2019-07-18 Eddie HungCheck if RHS is empty first
2019-07-18 Eddie HungMake consistent
2019-07-18 Eddie HungDo not autoremove ffP aor muxP
2019-07-18 Eddie HungImprove pattern matcher to match subsets of $dffe?...
2019-07-18 Eddie HungImprove A/B reg packing
2019-07-18 Eddie HungDo not autoremove A/B registers since they might have...
2019-07-18 Eddie HungFix xilinx_dsp index cast
2019-07-18 Eddie HungFix signed multiplier decomposition
2019-07-18 Eddie HungUse single DSP_SIGNEDONLY macro
2019-07-18 David ShahMerge pull request #1208 from ZirconiumX/intel_cleanups
2019-07-18 Dan Ravensloftsynth_intel: Use stringf
2019-07-18 Eddie HungWorking for unsigned
2019-07-18 David ShahMerge pull request #1207 from ZirconiumX/intel_new_pass...
2019-07-18 Dan Ravensloftsynth_intel: s/not family/no family/
2019-07-18 Eddie HungCleanup
2019-07-18 Dan Ravensloftsynth_intel: revert change to run_max10
2019-07-18 Ben Widawskyintel_synth: Fix help message
2019-07-18 Ben Widawskyintel_synth: Small code cleanup to remove if ladder
2019-07-18 Ben Widawskyintel_synth: Make family explicit and match
2019-07-18 Ben Widawskyintel_synth: Minor code cleanups
2019-07-18 Dan Ravensloftsynth_intel: rename for consistency with #1184
2019-07-18 Eddie HungWrong wildcard symbol
2019-07-18 Eddie HungMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into...
2019-07-18 Clifford WolfMerge pull request #1184 from whitequark/synth-better...
2019-07-18 Clifford WolfMerge pull request #1203 from whitequark/write_verilog...
2019-07-18 David Shahmul2dsp: Lower partial products always have unsigned...
2019-07-17 Eddie HungMake all operands signed
2019-07-17 Eddie HungUpdate comment
2019-07-17 Eddie HungPattern matcher to check pool of bits, not exactly
2019-07-17 Eddie HungFix mul2dsp signedness
2019-07-17 Eddie HungA_SIGNED == B_SIGNED so flip both
2019-07-17 Eddie HungSigSpec::remove_const() to return SigSpec&
2019-07-17 Clifford WolfRemove old $pmux_safe code from write_verilog
2019-07-17 David ShahMerge pull request #1204 from smunaut/fix_1187
2019-07-16 Eddie HungAdd DSP_{A,B}_SIGNEDONLY macro
2019-07-16 Eddie HungSignedness
2019-07-16 Eddie HungSigned extension
2019-07-16 Sylvain Munautice40: Adapt the relut process passes to the new $lut...
2019-07-16 Eddie HungRevert drop down to 24x16 multipliers for all
2019-07-16 Eddie HungMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into...
2019-07-16 Eddie HungAdd support {A,B,P}REG packing
2019-07-16 Eddie HungSigSpec::extract to allow negative length
2019-07-16 Eddie HungAdd support for {A,B,P}REG in DSP48E1
2019-07-16 whitequarkwrite_verilog: dump zero width constants correctly.
2019-07-16 Eddie HungMerge pull request #1202 from YosysHQ/cmp2lut_lut6
2019-07-16 whitequarksynth_ecp5: rename dram to lutram everywhere.
2019-07-16 whitequarksynth_{ice40,ecp5}: more sensible pass label naming.
2019-07-16 Eddie Hunggen_lut to return correctly sized LUT mask
2019-07-16 Eddie HungForgot to commit
2019-07-16 Eddie HungAdd tests for cmp2lut on LUT6
2019-07-16 David Shahxilinx: Add correct signed behaviour to DSP48E1 model
2019-07-16 Eddie HungMerge pull request #1188 from YosysHQ/eddie/abc9_push_i...
2019-07-16 Eddie HungMerge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
2019-07-16 David Shahxilinx: Treat DSP48E1 as 24x17 unsigned for now (actual...
2019-07-16 David Shahmul2dsp: Fix edge case where Y_WIDTH is less than B_WID...
2019-07-16 David Shahmul2dsp: Fix indentation
2019-07-16 Clifford WolfMerge pull request #1200 from mmicko/fix_typo_liberty_cc
2019-07-16 Clifford WolfMerge pull request #1199 from mmicko/extract_fa_fix
2019-07-16 Miodrag MilanovicFix typo, double "of"
2019-07-16 Miodrag MilanovicFix check logic in extract_fa
2019-07-15 Eddie HungDo not swap if equals
2019-07-15 Eddie HungSigSpec::extend_u0() to return *this
2019-07-15 Eddie HungOops forgot these files
2019-07-15 Eddie HungAdd xilinx_dsp for register packing
2019-07-15 Eddie HungOUT port to Y in generic DSP
2019-07-15 Eddie HungMove DSP mapping back out to dsp_map.v
2019-07-15 Eddie HungMerge pull request #1196 from YosysHQ/eddie/fix1178
2019-07-15 Eddie Hung$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per ...
2019-07-15 Eddie HungOnly swap if B_WIDTH > A_WIDTH
2019-07-15 Eddie HungTidy up
2019-07-15 Eddie HungMove DSP48E1 model out of cells_xtra, initial multiply...
2019-07-15 Clifford WolfMerge pull request #1189 from YosysHQ/eddie/fix1151
2019-07-15 Clifford WolfMerge pull request #1190 from YosysHQ/eddie/fix_1099
2019-07-15 Clifford WolfMerge pull request #1191 from whitequark/opt_lut-log_debug
2019-07-15 Clifford WolfMerge pull request #1195 from Roman-Parise/master
2019-07-15 Clifford WolfMerge pull request #1197 from nakengelhardt/handle...
2019-07-15 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-07-15 Eddie HungRevert "Add log_checkpoint function and use it in opt_m...
2019-07-15 N. Engelhardtsmt: handle failure of setrlimit syscall
2019-07-15 Eddie HungRevert "Fix first divergence in #1178"
2019-07-15 Eddie HungMerge branch 'master' into eddie/fix1178
next