nmigen.git
2018-12-26 whitequarkhdl.dsl: implement FSM.
2018-12-26 whitequarkback.rtlil: clarify $verilog_initial_trigger behavior...
2018-12-24 whitequarkback.rtlil: unbreak d47c1f8a.
2018-12-24 whitequarkhdl.mem: allow omitting memory simulation logic.
2018-12-24 whitequarkback.rtlil: use one $meminit cell, not one per word.
2018-12-24 whitequarkhdl.xfrm, back.rtlil: implement and use LHSGroupFilter.
2018-12-24 whitequarkhdl.xfrm: implement SwitchCleaner, for pruning empty...
2018-12-24 whitequarkback.rtlil: always output negative values as two's...
2018-12-23 whitequarkback.rtlil: emit dummy logic to work around Verilog...
2018-12-23 whitequarkback.rtlil: do not translate empty fragments.
2018-12-23 whitequarkback.rtlil: only translate switch tests once.
2018-12-23 whitequarkcli: generate: guess file type from extension.
2018-12-23 whitequarkback.rtlil: fix swapped operands in mux codegen.
2018-12-23 whitequarkcli: new module, for basic design generaton/simulation.
2018-12-22 whitequarkhdl.xfrm: avoid cycles in union-find graph in LHSGroupA...
2018-12-22 whitequarkcompat.genlib.fsm: fix naming for non-Signal LHS.
2018-12-22 whitequarkhdl.ir: flatten hierarchy based on memory accesses...
2018-12-22 whitequarkhdl.ir: factor out _merge_subfragment. NFC.
2018-12-22 whitequarkback.rtlil: split processes as finely as possible.
2018-12-22 whitequarkback.rtlil: remove useless condition. NFC.
2018-12-22 whitequarkhdl.xfrm: implement LHSGroupAnalyzer.
2018-12-22 whitequarkhdl.xfrm: Abstract*Transformer→*Visitor
2018-12-22 whitequarkback.rtlil: always initialize the entire memory.
2018-12-22 whitequarkcompat: use nicer names for next_value/next_value_ce...
2018-12-22 whitequarkhdl.mem: allow changing init value after creating memory.
2018-12-22 whitequarkback.verilog: do not rename internal signals.
2018-12-22 whitequarkcompat: fix confusing naming for memory port address...
2018-12-22 whitequarkhdl.ir: fix port propagation between siblings, in the...
2018-12-22 whitequarkcompat: do not finalize native submodules twice.
2018-12-21 whitequarkhdl.mem: use more informative signal naming for ports.
2018-12-21 whitequarkhdl.ir: fix port propagation between siblings.
2018-12-21 whitequarkcompat: provide verilog.convert shim.
2018-12-21 whitequarkhdl.ir: do not flatten instances or collect ports from...
2018-12-21 whitequarkcompat: provide Memory shim.
2018-12-21 whitequarkhdl.mem: ensure transparent read port model has correct...
2018-12-21 whitequarkback.pysim: handle out of bounds ArrayProxy indexes.
2018-12-21 whitequarkback.pysim: give numeric names to unnamed subfragments...
2018-12-21 whitequarkhdl.mem: use different naming for array signals.
2018-12-21 whitequarkhdl.mem: add simulation model for memory.
2018-12-21 whitequarkback.pysim: fix an issue with too few funclet slots.
2018-12-21 whitequarkhdl.mem: add tests for all error conditions.
2018-12-21 whitequarkhdl.mem: tie rdport.en high for asynchronous or transpa...
2018-12-21 whitequarkback.rtlil: more consistent prefixing for subfragment...
2018-12-21 whitequarkhdl.ir: correctly handle named output and inout ports.
2018-12-21 whitequarkback.rtlil: implement memories.
2018-12-21 whitequarkhdl.mem: implement memories.
2018-12-21 whitequarkback.rtlil: explicitly pad constants with zeroes.
2018-12-21 whitequarkback.rtlil: fix translation of Cat.
2018-12-20 whitequarkir: allow non-Signals in Instance ports.
2018-12-19 whitequarksetup: update pyvcd dependency, for var_type="string".
2018-12-18 whitequarkcompat: import genlib.record from Migen.
2018-12-18 whitequarkcompat: add wrappers for Slice.stop, Cat.l, _ArrayProxy...
2018-12-18 whitequarkhdl.ast: Cat.{operands→parts}
2018-12-18 whitequarkback.pysim: implement *.
2018-12-18 whitequarktest.sim: add tests for sync functionality and errors.
2018-12-18 whitequarkback.pysim: eliminate most dictionary lookups.
2018-12-18 whitequarkhdl.ast, hdl.xfrm: various microoptimizations to speed...
2018-12-18 whitequarkback.pysim: use arrays instead of dicts for signal...
2018-12-18 whitequarkback.pysim: naming. NFC.
2018-12-18 whitequarkback.pysim: fix an off-by-1 in add_sync_process().
2018-12-18 whitequarkback.pysim: trigger processes waiting on Tick() exactly...
2018-12-18 whitequarkback.pysim: continue running simulator processes until...
2018-12-18 whitequarkTravis: cache Yosys installation explicitly.
2018-12-17 whitequarkfhdl.ir: add black-box fragments, fragment parameters...
2018-12-17 whitequarkTravis: build and cache Yosys.
2018-12-17 whitequarkhdl, back: add and use SignalSet/SignalDict.
2018-12-17 whitequarkhdl.ast: factor out _MappedKeyDict, _MappedKeySet....
2018-12-17 whitequarkback.rtlil: update for Yosys master.
2018-12-17 whitequarkback.rtlil: implement Array.
2018-12-17 whitequarkback.rtlil: implement Part.
2018-12-16 whitequarkback.rtlil: handle reset_less domains.
2018-12-16 whitequarkhdl.dsl: add clock domain support.
2018-12-16 whitequarkhdl.dsl: cleanup. NFC.
2018-12-16 whitequarkback.rtlil: extract _StatementCompiler. NFC.
2018-12-16 whitequarkback.rtlil: simplify. NFC.
2018-12-16 whitequarkback.rtlil: properly escape strings in attributes.
2018-12-16 whitequarkREADME: mention Yosys requirement.
2018-12-16 whitequarkback.rtlil: prepare for Yosys sigspec slicing improvements.
2018-12-16 whitequarkcompat.fhdl.structure: only convert to bool in If/Elif...
2018-12-16 whitequarkback.rtlil: avoid illegal slices.
2018-12-16 whitequarkback.rtlil: use slicing to match shape when reducing...
2018-12-16 whitequarkback.rtlil: don't emit a slice if all bits are used.
2018-12-16 whitequarkback.rtlil: reorganize value compiler into LHS/RHS.
2018-12-16 whitequarkback.rtlil: fix naming. NFC.
2018-12-16 whitequarkhdl.xfrm: separate AST traversal from AST identity...
2018-12-16 whitequarkcompat.fhdl: reexport Array.
2018-12-16 whitequarkback.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
2018-12-15 whitequarktest.sim: generalize assertOperator. NFC.
2018-12-15 whitequarkback.pysim: add (stub) LHSValueCompiler.
2018-12-15 whitequarkback.pysim: implement Part.
2018-12-15 whitequarkexamples: rename clkdiv/ctrl to ctr/ctr_ce.
2018-12-15 whitequarkdoc: update COMPAT_SUMMARY.
2018-12-15 whitequarkback.pysim: implement ArrayProxy.
2018-12-15 whitequarkhdl.ast: implement Array and ArrayProxy.
2018-12-15 whitequarkLower Python version requirement to 3.6.
2018-12-15 whitequarkhdl: appropriately rename tests. NFC.
2018-12-15 whitequarkhdl.ast: improve ClockSignal, ResetSignal documentation.
2018-12-15 whitequarkRename fhdl→hdl, genlib→lib.
2018-12-15 whitequarkMove star imports to make `from nmigen import *` usable.
2018-12-15 whitequarkdoc: fix some Markdown awkwardness.
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