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yosys.git
2015-01-24
Clifford Wolf
Added #ifdef NDEBUG for log_assert()
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2015-01-24
Clifford Wolf
Fixed xilinx FDSE sim model
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2015-01-23
Clifford Wolf
Various equiv_* improvements
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2015-01-23
Clifford Wolf
Added dict/pool.sort()
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2015-01-22
Clifford Wolf
Improvements in equiv_make, equiv_induct
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2015-01-22
Clifford Wolf
Improved xdot calling
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2015-01-22
Clifford Wolf
Added equiv_induct
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2015-01-22
Clifford Wolf
Various equiv_simple improvements
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2015-01-22
Clifford Wolf
Moved equiv stuff to passes/equiv/
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2015-01-21
Clifford Wolf
Progress in equiv_simple
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2015-01-21
Clifford Wolf
Fixed opt_muxtree performance bug
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2015-01-20
Clifford Wolf
Faster "make clean-abc"
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2015-01-20
Clifford Wolf
README stuff
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2015-01-19
Clifford Wolf
Added equiv_simple
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2015-01-19
Clifford Wolf
Added equiv_status
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2015-01-19
Clifford Wolf
Added equiv_make command
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2015-01-19
Clifford Wolf
Added $equiv cell type
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2015-01-18
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-01-18
Clifford Wolf
Various cleanups in xilinx techlib
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2015-01-18
Clifford Wolf
Refactoring of memory_bram and xilinx brams
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2015-01-18
Clifford Wolf
Merge pull request #47 from mschmoelzer/master
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2015-01-18
Martin Schmölzer
Add "echo-yosys-ver" and "echo-git-rev" Makefile targets.
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2015-01-18
Clifford Wolf
improvements in muxtree/select_leaves test
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2015-01-18
Clifford Wolf
Improvements in opt_muxtree
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2015-01-18
Clifford Wolf
More opt_muxtree cleanups
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2015-01-18
Clifford Wolf
Added hashlib::idict<>
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2015-01-18
Clifford Wolf
Various cleanups and improvements in opt_muxtree
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2015-01-17
Clifford Wolf
Added synth_xilinx -retime -flatten
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2015-01-17
Clifford Wolf
Added support for memories to flatten (techmap)
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2015-01-17
Clifford Wolf
Added MUXCY and XORCY support to synth_xilinx
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2015-01-17
Clifford Wolf
Fixed a bug in opt_muxtree for "mux forests"
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2015-01-17
Clifford Wolf
Improved opt_muxtree
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2015-01-17
Clifford Wolf
Optimizing no-op cell->setPort()
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2015-01-16
Clifford Wolf
Bugfix in dff2dffe
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2015-01-16
Clifford Wolf
Added cells.lib
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2015-01-16
Clifford Wolf
Added dff2dffe to synth_xilinx
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2015-01-16
Clifford Wolf
Added more FF types to xilinx/cells.v
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2015-01-16
Clifford Wolf
Fixed xilinx bram clock inverted config
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2015-01-16
Clifford Wolf
Added FF cells to xilinx/cells_sim.v
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2015-01-15
Clifford Wolf
Added Xilinx MUXF7 and MUXF8 support
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2015-01-15
Clifford Wolf
Added "abc -lut w1:w2"
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2015-01-15
Clifford Wolf
Fixed handling of foo.__TECHMAP_...
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2015-01-15
Clifford Wolf
Ignoring more system task and functions
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2015-01-15
Clifford Wolf
Fixed handling of "input foo; reg [0:0] foo;"
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2015-01-15
Clifford Wolf
Consolidate "Blocking assignment to memory.." msgs...
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2015-01-13
Clifford Wolf
Various cleanups in synth_xilinx command
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2015-01-13
Clifford Wolf
Re-enabled mux->and/or transform (and fixed lm32 in...
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2015-01-13
Clifford Wolf
Tiny fix in vcdcd.pl
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2015-01-13
Clifford Wolf
Small Makefile typo fix
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2015-01-09
Clifford Wolf
Only enable code coverage counters on linux
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2015-01-08
Clifford Wolf
Merge pull request #46 from utzig/master
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2015-01-08
Fabio Utzig
Enable use of homebrew's provided bison if available
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2015-01-08
Fabio Utzig
Enable bison to be customized
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2015-01-08
Fabio Utzig
Add homebrew's libffi paths
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2015-01-08
Fabio Utzig
Add homebrew's readline paths
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2015-01-07
Clifford Wolf
Added add_share_file Makefile macro
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2015-01-07
Clifford Wolf
added minimalistic xilinx sim models
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2015-01-07
Clifford Wolf
disabled problematic mux -> and/or transform
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2015-01-07
Clifford Wolf
More Xilinx bram cleanups
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2015-01-07
Clifford Wolf
Cleanups in xilinx bram descriptions
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2015-01-06
Clifford Wolf
memory_bram hotfix for memories with width 1
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2015-01-06
Clifford Wolf
Xilinx RAMB36/RAMB18 memory_bram support complete
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2015-01-06
Clifford Wolf
Towards Xilinx bram support
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2015-01-06
Clifford Wolf
small fix in xilinx/brams.v
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2015-01-06
Clifford Wolf
fixed compiler warning on non-linux archs
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2015-01-06
Clifford Wolf
removed old debug code
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2015-01-06
Clifford Wolf
hashlib iterator fix
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2015-01-06
Clifford Wolf
build fix for mxe
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2015-01-06
Clifford Wolf
Towards Xilinx bram support
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2015-01-06
Clifford Wolf
Various small improvements to synth_xilinx
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2015-01-06
Clifford Wolf
Towards Xilinx bram support
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2015-01-06
Clifford Wolf
Towards Xilinx bram support
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2015-01-05
Clifford Wolf
dict<> ref vs insert bugfix
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2015-01-05
Clifford Wolf
Towards Xilinx bram support
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2015-01-04
Clifford Wolf
Towards Xilinx bram support
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2015-01-04
Clifford Wolf
Added memory_bram "shuffle_enable" feature
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2015-01-04
Clifford Wolf
Removed left over debug code from memory_bram
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2015-01-04
Clifford Wolf
Fixed pattern matching in "hierarchy -generate"
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2015-01-03
Clifford Wolf
Print non-errors to stdout
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2015-01-03
Clifford Wolf
Added "memory -bram"
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2015-01-03
Clifford Wolf
Added memory_bram 'or_next_if_better' feature
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2015-01-03
Clifford Wolf
memory_bram transp support
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2015-01-03
Clifford Wolf
Progress in memory_bram
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2015-01-02
Clifford Wolf
Cosmetic changes in verilog output format
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2015-01-02
Clifford Wolf
Added proper clkpol support to memory_bram
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2015-01-02
Clifford Wolf
Fixes and improvements in bram test
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2015-01-02
Clifford Wolf
Progress in bram testbench
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2015-01-02
Clifford Wolf
Define YOSYS and SYNTHESIS in preproc
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2015-01-02
Clifford Wolf
New $mem simlib model
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2015-01-02
Clifford Wolf
Progress in memory_bram
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2015-01-01
Clifford Wolf
Progress in memory_bram
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2015-01-01
Clifford Wolf
Progress in bram testbench
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2015-01-01
Clifford Wolf
Bram testbench (incomplete)
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2015-01-01
Clifford Wolf
Progress in memory_bram
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2015-01-01
Clifford Wolf
Fixed memory->start_offset handling
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2015-01-01
Clifford Wolf
Progress in memory_bram
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2015-01-01
Clifford Wolf
Removed SigSpec::extend_xx() api
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2014-12-31
Clifford Wolf
Progress in memory_bram
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2014-12-31
Clifford Wolf
Added memory_bram (not functional yet)
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2014-12-31
Clifford Wolf
Added hashlib .count(key, iterator) and it1 < it2
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