yosys.git
2019-07-11 Eddie HungSimplify to $__ABC_ASYNC box
2019-07-11 Eddie Hung$__ABC_FD_ASYNC_MUX.Q -> Y
2019-07-11 Eddie HungMissing debug message
2019-07-11 Eddie HungError out if abc9 not called with -lut or -luts
2019-07-11 Eddie HungCount $_NOT_ cells turned into $luts
2019-07-11 Eddie HungWIP for fixing partitioning, temporarily do not partition
2019-07-11 Eddie HungRestore from master
2019-07-11 Eddie HungAnother typo
2019-07-11 Eddie Hungabc_flop to also get topologically sorted
2019-07-11 Eddie Hungwrite_verilog with *.v extension
2019-07-11 Eddie HungFix clk_pol for FD*_1
2019-07-11 Eddie HungAnother typo
2019-07-11 Eddie HungAnother typo
2019-07-11 Eddie HungFix spacing
2019-07-11 Eddie HungUse \$currQ
2019-07-11 Eddie HungRemove -retime from abc9, revert to abc behav with...
2019-07-11 Eddie HungPreserve all parameters, plus some extra ones for clk...
2019-07-11 Eddie HungSmall opt
2019-07-11 Eddie HungChange how to specify flops to ABC again
2019-07-11 Eddie HungUse split_tokens()
2019-07-11 Eddie HungRemove params from FD*_1 variants
2019-07-11 Eddie HungFix typo, and have !{PRE,CLR} behave as CE
2019-07-11 Eddie HungMove ABC FF stuff to abc_ff.v; add support for other...
2019-07-10 Eddie HungUncomment IS_C_INVERTED parameter
2019-07-10 Eddie Hungsynth_xilinx's map_cells stage to techmap ff_map.v
2019-07-10 Eddie HungFix box numbering
2019-07-10 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-07-10 Eddie HungMerge pull request #1180 from YosysHQ/eddie/no_abc9_retime
2019-07-10 Eddie HungMerge pull request #1148 from YosysHQ/xc7mux
2019-07-10 Eddie HungError out if -abc9 and -retime specified
2019-07-10 Eddie HungAdd some spacing
2019-07-10 Eddie HungAdd some ASCII art explaining mux decomposition
2019-07-10 Clifford WolfMerge pull request #1177 from YosysHQ/clifford/async
2019-07-10 Eddie HungCall muxpack and pmux2shiftx before cmp2lut
2019-07-09 Eddie HungRestore opt_clean back to original place
2019-07-09 Eddie HungRestore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
2019-07-09 David Shahsynth_ecp5: Fix typo in copyright header
2019-07-09 Clifford WolfMerge pull request #1174 from YosysHQ/eddie/fix1173
2019-07-09 Clifford WolfMerge pull request #1175 from whitequark/write_verilog...
2019-07-09 Clifford WolfFix tests/various/async FFL test
2019-07-09 Clifford WolfImprove tests/various/async, disable failing ffl test
2019-07-09 Eddie HungExtend using A[1] to preserve don't care
2019-07-09 Eddie HungMerge pull request #1171 from YosysHQ/revert-1166-eddie...
2019-07-09 Eddie HungMerge remote-tracking branch 'origin/eddie/fix1173...
2019-07-09 whitequarkwrite_verilog: fix placement of case attributes. NFC.
2019-07-09 Eddie HungIncrement _TECHMAP_BITS_CONNMAP_ by one since counting...
2019-07-09 Clifford WolfAdd tests/various/async.{sh,v}
2019-07-09 Clifford WolfImprove tests/various/run-test.sh
2019-07-09 Clifford WolfAdd tests/simple_abc9/.gitignore
2019-07-09 Eddie HungExtend during mux decomposition with 1'bx
2019-07-09 Eddie HungFix typo and comments
2019-07-09 Eddie HungMerge pull request #1170 from YosysHQ/eddie/fix_double_...
2019-07-09 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-07-09 Eddie Hungsynth_xilinx to call commands of synth -coarse directly
2019-07-09 Eddie HungRevert "synth_xilinx to call "synth -run coarse" with...
2019-07-09 Eddie HungRevert "Add "synth -keepdc" option"
2019-07-09 Eddie HungRename __builtin_bswap32 -> bswap32
2019-07-09 Eddie HungFix spacing
2019-07-09 Eddie HungFix spacing
2019-07-09 Clifford WolfMerge pull request #1168 from whitequark/bugpoint-processes
2019-07-09 Clifford WolfMerge pull request #1169 from whitequark/more-proc...
2019-07-09 Clifford WolfMerge pull request #1163 from whitequark/more-case...
2019-07-09 Clifford WolfMerge pull request #1162 from whitequark/rtlil-case...
2019-07-09 Clifford WolfMerge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup
2019-07-09 whitequarkproc_prune: promote assigns to module connections when...
2019-07-09 whitequarkproc_prune: new pass.
2019-07-09 whitequarkbugpoint: add -assigns and -updates options.
2019-07-09 whitequarkproc_clean: add -quiet option.
2019-07-09 Eddie HungDecompose mux inputs in delay-orientated (rather than...
2019-07-09 Eddie HungDo not call opt -mux_undef (part of -full) before muxcover
2019-07-09 Eddie HungAdd one more comment
2019-07-09 Eddie HungLess thinking
2019-07-09 Eddie HungReword
2019-07-09 Eddie HungMerge pull request #1166 from YosysHQ/eddie/synth_keepdc
2019-07-09 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-07-09 Eddie Hungsynth_xilinx to call "synth -run coarse" with "-keepdc"
2019-07-09 Eddie HungMerge remote-tracking branch 'origin/eddie/synth_keepdc...
2019-07-09 Eddie HungClarify script -scriptwire doc
2019-07-09 Eddie HungAdd synth -keepdc to CHANGELOG
2019-07-09 Eddie HungClarify 'wreduce -keepdc' doc
2019-07-09 Eddie HungAdd synth -keepdc option
2019-07-09 Eddie HungMap $__XILINX_SHIFTX in a more balanced manner
2019-07-09 Eddie HungCapitalisation
2019-07-09 Eddie HungAdd synth_xilinx -widemux recommended value
2019-07-08 Eddie HungMerge pull request #1164 from YosysHQ/eddie/muxcover_mux2
2019-07-08 David ShahMerge pull request #1160 from ZirconiumX/cyclone_v
2019-07-08 Eddie HungUpdate muxcover doc as per @ZirconiumX
2019-07-08 Eddie HungFixes for 2:1 muxes
2019-07-08 Eddie Hungsynth_xilinx -widemux=2 is minimum now
2019-07-08 Eddie HungParametric muxcover costs as per @daveshah1
2019-07-08 Eddie HungMerge remote-tracking branch 'origin/eddie/muxcover_mux...
2019-07-08 Eddie Hungatoi -> stoi
2019-07-08 Eddie HungAdd muxcover -mux2=cost option
2019-07-08 Eddie Hungatoi -> stoi as per @daveshah1
2019-07-08 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-07-08 whitequarkverilog_backend: dump attributes on SwitchRule.
2019-07-08 whitequarkproc_mux: consider \src attribute on CaseRule.
2019-07-08 whitequarkverilog_backend: dump attributes on CaseRule, as comments.
2019-07-08 whitequarkgenrtlil: emit \src attribute on CaseRule.
2019-07-08 whitequarkAllow attributes on individual switch cases in RTLIL.
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