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yosys.git
2019-08-08
Eddie Hung
Disable $dffe
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2019-08-08
Eddie Hung
INMODE is 5 bits
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2019-08-08
Eddie Hung
Fix copy-pasta typo
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2019-08-08
David Shah
ecp5: Replace '-dsp' with inverse logic '-nodsp' to...
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2019-08-08
David Shah
ecp5: Bring up to date with mul2dsp changes
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2019-08-08
David Shah
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into...
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2019-08-08
David Shah
DSP48E1 sim model: add SIMD tests
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2019-08-08
David Shah
DSP48E1 model: test CE inputs
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2019-08-08
David Shah
DSP48E1 sim model: fix seq tests and add preadder tests
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2019-08-08
David Shah
DSP48E1 sim model: seq test working
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2019-08-08
David Shah
DSP48E1 sim model: Comb, no pre-adder, mode working
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2019-08-08
David Shah
[wip] sim model testing
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2019-08-08
David Shah
[wip] sim model testing
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2019-08-07
Eddie Hung
Fix compile error
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2019-08-07
Eddie Hung
Run "opt_expr -fine" instead of "wreduce" due to #1213
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2019-08-07
Eddie Hung
Do not SigSpec::extract() beyond bounds
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2019-08-07
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-08-07
Eddie Hung
Do not pack registers if (* keep *)
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2019-08-07
Eddie Hung
Merge pull request #1248 from YosysHQ/eddie/abc9_speedup
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2019-08-07
Eddie Hung
Add comment
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2019-08-07
Eddie Hung
Revert "Add TODO"
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2019-08-07
Eddie Hung
Add TODO
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2019-08-07
Eddie Hung
Compute box_lookup just once
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2019-08-07
Eddie Hung
Run "clean" on mapped_mod in its own design
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2019-08-07
Eddie Hung
Run "clean -purge" on holes_module in its own design
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2019-08-07
David Shah
Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes
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2019-08-07
David Shah
ecp5: Make cells_sim.v consistent with nextpnr
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2019-08-07
Clifford Wolf
Merge pull request #1213 from YosysHQ/eddie/wreduce_add
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2019-08-07
David Shah
[wip] DSP48E1 sim model improvements
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2019-08-07
Clifford Wolf
Merge pull request #1240 from ucb-bar/firrtl-properties...
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2019-08-07
Clifford Wolf
Merge pull request #1249 from mmicko/anlogic_fix
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2019-08-07
Clifford Wolf
Merge pull request #1252 from YosysHQ/clifford/fix1231
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2019-08-07
Clifford Wolf
Merge pull request #1253 from YosysHQ/clifford/check
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2019-08-07
Clifford Wolf
Merge pull request #1257 from YosysHQ/clifford/cellcosts
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2019-08-07
David Shah
Update CHANGELOG
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2019-08-07
David Shah
Merge pull request #1241 from YosysHQ/clifford/jsonfix
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2019-08-07
Clifford Wolf
Tweak default gate costs, cleanup "stat -tech cmos"
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2019-08-06
Clifford Wolf
Redesign of cell cost API
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2019-08-06
Eddie Hung
Add signed opt_expr tests
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2019-08-06
Eddie Hung
Add signed test
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2019-08-06
Eddie Hung
Move LSB-trimming functionality from wreduce to opt_expr
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2019-08-06
Eddie Hung
Add SigSpec::extract_end() convenience function
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2019-08-06
Eddie Hung
Restore original SigSpec::extract()
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2019-08-06
Eddie Hung
Move LSB tests from wreduce to opt_expr
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2019-08-06
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-06
David Shah
Merge pull request #1232 from YosysHQ/dave/write_gzip
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2019-08-06
David Shah
[wip] DSP48E1 sim model improvements
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2019-08-06
Clifford Wolf
Be less aggressive with running design->check()
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2019-08-06
David Shah
Add test for writing gzip-compressed files
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2019-08-06
David Shah
Add support for writing gzip-compressed files
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2019-08-06
Clifford Wolf
Fix handling of functions/tasks without top-level begin...
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2019-08-06
Clifford Wolf
Merge pull request #1251 from YosysHQ/clifford/nmux
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2019-08-06
David Shah
[wip] DSP48E1 sim model improvements
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2019-08-06
Clifford Wolf
Add $_NMUX_, add "abc -g cmos", add proper cmos cell...
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2019-08-03
Miodrag Milanovic
anlogic : Fix alu mapping
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2019-08-03
whitequark
Merge pull request #1242 from jfng/fix-proc_prune-partial
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2019-08-02
Clifford Wolf
Merge pull request #1238 from mmicko/vsbuild_fix
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2019-08-02
Clifford Wolf
Merge pull request #1239 from mmicko/mingw_fix
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2019-08-01
Eddie Hung
Add comment about supporting $dffe in ice40_dsp
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2019-08-01
Eddie Hung
Pack P register properly
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2019-08-01
Eddie Hung
Trim Y_WIDTH
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2019-08-01
Eddie Hung
Add DSP_SIGNEDONLY back
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2019-08-01
Eddie Hung
DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH
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2019-08-01
Eddie Hung
Change $__softmul back to $mul
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2019-08-01
Eddie Hung
Cope with sign extension in mul2dsp
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2019-08-01
Eddie Hung
Revert "Do not do sign extension in techmap; let packer...
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2019-08-01
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-08-01
Eddie Hung
Fix B_WIDTH > DSP_B_MAXWIDTH case
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2019-08-01
Eddie Hung
CO is sign extension only if signed multiplier
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2019-08-01
Eddie Hung
Fix typo
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2019-08-01
Eddie Hung
Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map
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2019-08-01
Miodrag Milanovic
Fix linking issue for new mxe and pthread
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2019-08-01
Miodrag Milanovic
Fix yosys linking for mxe
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2019-08-01
Miodrag Milanovic
New mxe hacks needed to support 2ca237e
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2019-08-01
Miodrag Milanovic
Fix formatting for msys2 mingw build using GetSize
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2019-08-01
Jean-François...
proc_prune: Promote partially redundant assignments.
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2019-08-01
Clifford Wolf
Update JSON front-end to process new attr/param encoding
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2019-08-01
Clifford Wolf
Implement improved JSON attr/param encoding
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2019-07-31
Eddie Hung
Do not compute sign bit if result is zero
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2019-07-31
Eddie Hung
For signed multipliers, compute sign bit separately...
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2019-07-31
Eddie Hung
Restore old CO behaviour
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2019-07-31
Eddie Hung
Helper: SigSpec::operator[] to accept negative indices
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2019-07-31
Jim Lawson
Support explicit FIRRTL properties for better accommoda...
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2019-07-31
Clifford Wolf
Merge pull request #1233 from YosysHQ/clifford/defer
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2019-07-31
Miodrag Milanovic
Visual Studio build fix
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2019-07-30
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-07-29
Eddie Hung
RST -> RSTBRST for RAMB8BWER
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2019-07-29
Eddie Hung
Merge pull request #1228 from YosysHQ/dave/yy_buf_size
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2019-07-29
David Shah
Merge pull request #1234 from mmicko/fix_gzip_no_exist
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2019-07-29
Miodrag Milanovic
Fix case when file does not exist
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2019-07-29
Clifford Wolf
Update README to use "read" instead of "read_verilog"
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2019-07-29
Clifford Wolf
Call "read_verilog" with -defer from "read"
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2019-07-27
David Shah
Merge pull request #1226 from YosysHQ/dave/gzip
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2019-07-26
Eddie Hung
Fix spacing
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2019-07-26
Eddie Hung
Update test_autotb doc to reflect default value of...
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2019-07-26
Eddie Hung
Add doc for "test_autotb -seed" option
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2019-07-26
Eddie Hung
Pop the CO bit from O
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2019-07-26
Eddie Hung
Allow adders/accumulators with 33 bits using CO output
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2019-07-26
David Shah
Update CHANGELOG
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2019-07-26
David Shah
verilog_lexer: Increase YY_BUF_SIZE to 65536
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