yosys.git
2019-06-21 Clifford WolfMerge pull request #1122 from YosysHQ/clifford/jsonports
2019-06-21 Clifford WolfAdded JSON upto and offset
2019-06-21 Clifford WolfMerge pull request #1121 from YosysHQ/ecp5-ccu2c-inv
2019-06-21 David Shahecp5: Improve mapping of $alu when BI is used
2019-06-21 Clifford WolfMerge pull request #1117 from bwidawsk/more-home
2019-06-21 Clifford WolfMerge pull request #1119 from YosysHQ/eddie/fix1118
2019-06-21 Clifford WolfMerge pull request #1116 from YosysHQ/eddie/fix1115
2019-06-21 Eddie HungFix gcc invalidation behaviour for write_aiger
2019-06-20 Eddie HungAdd test
2019-06-20 Eddie HungMake genvar a signed type
2019-06-20 Eddie HungAdd CHANGELOG entry
2019-06-20 Eddie HungExtend sign extension tests
2019-06-20 Eddie HungMaintain "is_unsized" state of constants
2019-06-20 Eddie HungRevert "Fix sign extension when sign is 1'bx"
2019-06-20 Ben WidawskyAdd a few more filename rewrites
2019-06-20 Eddie HungRemove leftover comment
2019-06-20 Eddie HungAdd test
2019-06-20 Eddie HungFix sign extension when sign is 1'bx
2019-06-20 Clifford WolfFix typo, fixes #1095
2019-06-20 Clifford WolfImprove shregmap help message, fixes #1113
2019-06-20 Clifford WolfUpdate some .gitignore files
2019-06-20 Clifford WolfFix typo
2019-06-20 Clifford WolfMerge branch 'towoe-unpacked_arrays'
2019-06-20 Clifford WolfAdd proper test for SV-style arrays
2019-06-20 Clifford WolfMerge branch 'unpacked_arrays' of https://github.com...
2019-06-19 Eddie HungMerge pull request #1111 from acw1251/help_summary_fixes
2019-06-19 acw1251Fixed small typo in ice40_unlut help summary
2019-06-19 acw1251Fixed the help summary line for a few commands
2019-06-19 Eddie HungFix bug in #1078, add entry to CHANGELOG
2019-06-19 Clifford WolfMerge pull request #1109 from YosysHQ/clifford/fix1106
2019-06-19 Clifford WolfAdd "read_verilog -pwires" feature, closes #1106
2019-06-19 Clifford WolfMerge pull request #1105 from YosysHQ/clifford/fixlogicinit
2019-06-19 Tobias WölfelUnpacked array declaration using size
2019-06-19 Clifford WolfMake tests/aiger less chatty
2019-06-19 Clifford WolfAdd defvalue test, minor autotest fixes for .sv files
2019-06-19 Clifford WolfUse input default values in hierarchy pass
2019-06-19 Clifford WolfAdd defaultvalue attribute
2019-06-19 Clifford WolfFix handling of "logic" variables with initial value
2019-06-19 Clifford WolfMerge pull request #1100 from bwidawsk/home
2019-06-19 Clifford WolfMerge pull request #1104 from whitequark/case-semantics
2019-06-19 whitequarkExplain exact semantics of switch and case rules in...
2019-06-19 whitequarkIn RTLIL::Module::check(), check process invariants.
2019-06-18 Ben WidawskySupport filename rewrite in backends
2019-06-18 Ben WidawskySupport ~ for home directory
2019-06-18 Clifford WolfMerge pull request #1086 from udif/pr_elab_sys_tasks2
2019-06-16 Clifford WolfAdd timescale and generated-by header to yosys-smtbmc...
2019-06-13 Serge BazanskiMerge pull request #829 from abdelrahmanhosny/master
2019-06-10 Udi FinkelsteinFixed brojen $error()/$info/$warning() on non-generate...
2019-06-10 Eddie HungAdd some more comments
2019-06-10 David ShahMerge pull request #1082 from corecode/u4k
2019-06-10 Simon Schubertice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR...
2019-06-08 Clifford WolfMerge pull request #1078 from YosysHQ/eddie/muxcover_costs
2019-06-07 Eddie HungFix spacing from spaces to tabs
2019-06-07 Clifford WolfMerge pull request #1079 from YosysHQ/eddie/fix_read_aiger
2019-06-07 Eddie HungAdd read_aiger to CHANGELOG
2019-06-07 Eddie HungFix spacing (entire file is wrong anyway, will fix...
2019-06-07 Eddie HungRemove unnecessary std::getline() for ASCII
2019-06-07 Eddie HungTest *.aag too, by using *.aig as reference
2019-06-07 Eddie HungFix read_aiger -- create zero driver, fix init width...
2019-06-07 Eddie HungUse ABC to convert from AIGER to Verilog
2019-06-07 Eddie HungUse ABC to convert AIGER to Verilog, then sat against...
2019-06-07 Eddie HungAdd symbols to AIGER test inputs for ABC
2019-06-07 Eddie HungAllow muxcover costs to be changed
2019-06-07 Clifford WolfMerge pull request #1077 from YosysHQ/clifford/pr983
2019-06-07 Clifford WolfRename implicit_ports.sv test to implicit_ports.v
2019-06-07 Clifford WolfFixes and cleanups in AST_TECALL handling
2019-06-07 Clifford WolfMerge branch 'pr_elab_sys_tasks' of https://github...
2019-06-07 Clifford WolfMerge branch 'tux3-implicit_named_connection'
2019-06-07 Clifford WolfMerge pull request #1076 from thasti/centos7-build-fix
2019-06-07 Clifford WolfCleanup tux3-implicit_named_connection
2019-06-07 Clifford WolfMerge branch 'implicit_named_connection' of https:...
2019-06-07 Stefan Biereigelremove boost/log/exceptions.hpp from wrapper generator
2019-06-06 tux3SystemVerilog support for implicit named port connections
2019-06-06 Clifford WolfMerge pull request #1060 from antmicro/parsing_attr_on_...
2019-06-06 David ShahMerge pull request #1073 from whitequark/ecp5-diamond-iob
2019-06-06 whitequarkECP5: implement all Diamond I/O buffer primitives.
2019-06-06 Clifford WolfMerge pull request #1071 from YosysHQ/eddie/fix_1070
2019-06-06 Clifford WolfMerge pull request #1072 from YosysHQ/eddie/fix_1069
2019-06-05 Eddie HungMissing doc for -tech xilinx in shregmap
2019-06-05 Eddie HungError out if no top module given before 'sim'
2019-06-05 Eddie HungFix typo in opt_rmdff
2019-06-05 Eddie HungMerge pull request #1067 from YosysHQ/clifford/fix1065
2019-06-05 Maciej KurcFixed memory leak.
2019-06-05 Clifford WolfMerge pull request #1066 from YosysHQ/clifford/fix1056
2019-06-05 Clifford WolfMajor rewrite of wire selection in setundef -init
2019-06-05 Clifford WolfIndent fix
2019-06-05 Clifford WolfMerge pull request #999 from jakobwenzel/setundefInitFix
2019-06-05 Clifford WolfFix typo in fmcombine log message, fixes #1063
2019-06-05 Clifford WolfSuppress driver-driver conflict warning for unknown...
2019-06-05 Clifford WolfRemove yosys_banner() from python wrapper init, fixes...
2019-06-04 Clifford WolfMerge pull request #1062 from tux3/patch-1
2019-06-04 Tux3README.md: Missing formatting for <tag>
2019-06-04 Maciej KurcMoved tests that fail with Icarus Verilog to /tests...
2019-06-04 Eddie HungMerge pull request #1061 from YosysHQ/eddie/techmap_and...
2019-06-04 Eddie HungRemove extra newline
2019-06-04 Eddie HungExecute techmap and arith_map simultaneously
2019-06-03 Maciej KurcAdded tests for attributes
2019-06-02 Clifford WolfOnly support Symbiotic EDA flavored Verific
2019-05-31 Maciej KurcAdded support for parsing attributes on port connections.
2019-05-31 Clifford WolfFix "tee" handling of log_streams
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