yosys.git
2019-08-07 Clifford WolfAutomatically prune init attributes in verific front...
2019-08-07 Clifford WolfMerge pull request #1213 from YosysHQ/eddie/wreduce_add
2019-08-07 Clifford WolfMerge pull request #1240 from ucb-bar/firrtl-properties...
2019-08-07 Clifford WolfMerge pull request #1249 from mmicko/anlogic_fix
2019-08-07 Clifford WolfMerge pull request #1252 from YosysHQ/clifford/fix1231
2019-08-07 Clifford WolfMerge pull request #1253 from YosysHQ/clifford/check
2019-08-07 Clifford WolfMerge pull request #1257 from YosysHQ/clifford/cellcosts
2019-08-07 David ShahUpdate CHANGELOG
2019-08-07 David ShahMerge pull request #1241 from YosysHQ/clifford/jsonfix
2019-08-07 Clifford WolfTweak default gate costs, cleanup "stat -tech cmos"
2019-08-06 Clifford WolfRedesign of cell cost API
2019-08-06 Eddie HungAdd signed opt_expr tests
2019-08-06 Eddie HungAdd signed test
2019-08-06 Eddie HungMove LSB-trimming functionality from wreduce to opt_expr
2019-08-06 Eddie HungAdd SigSpec::extract_end() convenience function
2019-08-06 Eddie HungRestore original SigSpec::extract()
2019-08-06 Eddie HungMove LSB tests from wreduce to opt_expr
2019-08-06 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-06 David ShahMerge pull request #1232 from YosysHQ/dave/write_gzip
2019-08-06 Clifford WolfBe less aggressive with running design->check()
2019-08-06 David ShahAdd test for writing gzip-compressed files
2019-08-06 David ShahAdd support for writing gzip-compressed files
2019-08-06 Clifford WolfFix handling of functions/tasks without top-level begin...
2019-08-06 Clifford WolfMerge pull request #1251 from YosysHQ/clifford/nmux
2019-08-06 Clifford WolfAdd $_NMUX_, add "abc -g cmos", add proper cmos cell...
2019-08-03 Miodrag Milanovicanlogic : Fix alu mapping
2019-08-03 whitequarkMerge pull request #1242 from jfng/fix-proc_prune-partial
2019-08-02 Clifford WolfMerge pull request #1238 from mmicko/vsbuild_fix
2019-08-02 Clifford WolfMerge pull request #1239 from mmicko/mingw_fix
2019-08-01 Eddie HungMerge pull request #1236 from YosysHQ/eddie/xc6s_brams_map
2019-08-01 Miodrag MilanovicFix linking issue for new mxe and pthread
2019-08-01 Miodrag MilanovicFix yosys linking for mxe
2019-08-01 Miodrag MilanovicNew mxe hacks needed to support 2ca237e
2019-08-01 Miodrag MilanovicFix formatting for msys2 mingw build using GetSize
2019-08-01 Jean-François... proc_prune: Promote partially redundant assignments.
2019-08-01 Clifford WolfUpdate JSON front-end to process new attr/param encoding
2019-08-01 Clifford WolfImplement improved JSON attr/param encoding
2019-07-31 Jim LawsonSupport explicit FIRRTL properties for better accommoda...
2019-07-31 Clifford WolfMerge pull request #1233 from YosysHQ/clifford/defer
2019-07-31 Miodrag MilanovicVisual Studio build fix
2019-07-30 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-07-29 Eddie HungRST -> RSTBRST for RAMB8BWER
2019-07-29 Eddie HungMerge pull request #1228 from YosysHQ/dave/yy_buf_size
2019-07-29 David ShahMerge pull request #1234 from mmicko/fix_gzip_no_exist
2019-07-29 Miodrag MilanovicFix case when file does not exist
2019-07-29 Clifford WolfUpdate README to use "read" instead of "read_verilog"
2019-07-29 Clifford WolfCall "read_verilog" with -defer from "read"
2019-07-27 David ShahMerge pull request #1226 from YosysHQ/dave/gzip
2019-07-26 David ShahUpdate CHANGELOG
2019-07-26 David Shahverilog_lexer: Increase YY_BUF_SIZE to 65536
2019-07-26 David ShahFix frontend auto-detection for gzipped input
2019-07-26 David ShahAdd support for reading gzip'd input files
2019-07-25 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-07-25 Eddie HungBump abc to fix &mfs bug
2019-07-25 Clifford WolfMerge branch 'ZirconiumX-synth_intel_m9k'
2019-07-25 Clifford WolfMerge pull request #1218 from ZirconiumX/synth_intel_iopads
2019-07-25 Clifford WolfMerge pull request #1219 from jakobwenzel/objIterator
2019-07-25 Eddie HungMerge pull request #1224 from YosysHQ/xilinx_fix_ff
2019-07-25 Jakob Wenzelreplaced std::iterator with using statements
2019-07-25 David Shahxilinx: Fix missing cell name underscore in cells_map.v
2019-07-24 Eddie HungMerge pull request #1222 from koriakin/s6-example
2019-07-24 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-07-24 Marcin KościelnickiAdd a simple example for Spartan 6
2019-07-24 Jakob Wenzelmade ObjectIterator extend std::iterator
2019-07-24 Dan Ravensloftintel: Make -noiopads the default
2019-07-23 Dan Ravensloftintel: Map M9K BRAM only on families that have it
2019-07-23 Eddie HungMerge pull request #1212 from YosysHQ/eddie/signed_ice4...
2019-07-22 Eddie HungMerge pull request #1214 from jakobwenzel/astmod_clone
2019-07-22 Jakob Wenzelinitialize noblackbox and nowb in AstModule::clone
2019-07-20 Clifford WolfAdd "stat -tech cmos"
2019-07-19 Eddie HungTry and fix again
2019-07-19 Eddie HungAdd another test
2019-07-19 Eddie HungDo not access beyond bounds
2019-07-19 Eddie HungAdd an SigSpec::at(offset, defval) convenience method
2019-07-19 Eddie HungWrap A and B in sigmap
2019-07-19 Eddie HungRemove "top" from message
2019-07-19 Eddie HungAlso optimise MSB of $sub
2019-07-19 Eddie HungAdd one more test with trimming Y_WIDTH of $sub
2019-07-19 Eddie HungBe more explicit
2019-07-19 Eddie Hungwreduce for $sub
2019-07-19 Eddie HungAdd tests for sub too
2019-07-19 Eddie HungAdd test
2019-07-19 Eddie HungSigSpec::extract to take negative lengths
2019-07-19 David Shahice40: Fix test_dsp_model.sh
2019-07-19 David Shahice40/cells_sim.v: Fix sign of J and K partial products
2019-07-19 David Shahice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
2019-07-19 Eddie HungAdd tests for all combinations of A and B signedness...
2019-07-19 Eddie HungDon't copy ref if exists already
2019-07-18 David ShahMerge pull request #1208 from ZirconiumX/intel_cleanups
2019-07-18 Dan Ravensloftsynth_intel: Use stringf
2019-07-18 David ShahMerge pull request #1207 from ZirconiumX/intel_new_pass...
2019-07-18 Dan Ravensloftsynth_intel: s/not family/no family/
2019-07-18 Dan Ravensloftsynth_intel: revert change to run_max10
2019-07-18 Ben Widawskyintel_synth: Fix help message
2019-07-18 Ben Widawskyintel_synth: Small code cleanup to remove if ladder
2019-07-18 Ben Widawskyintel_synth: Make family explicit and match
2019-07-18 Ben Widawskyintel_synth: Minor code cleanups
2019-07-18 Dan Ravensloftsynth_intel: rename for consistency with #1184
2019-07-18 Clifford WolfMerge pull request #1184 from whitequark/synth-better...
2019-07-18 Clifford WolfMerge pull request #1203 from whitequark/write_verilog...
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