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yosys.git
2019-02-17 Eddie Hungread_aiger to ignore line after ands for ascii, not... commit | commitdiff | tree
2019-02-17 Eddie HungOne more merge conflict commit | commitdiff | tree
2019-02-17 Eddie HungMerge branch 'dff_init' into read_aiger commit | commitdiff | tree
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init commit | commitdiff | tree
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger commit | commitdiff | tree
2019-02-17 Clifford WolfMerge pull request #811 from ucb-bar/firrtlfixes commit | commitdiff | tree
2019-02-15 Jim LawsonRemoved unused variables, functions. commit | commitdiff | tree
2019-02-15 Jim LawsonAppend (instead of over-writing) EXTRA_FLAGS commit | commitdiff | tree
2019-02-15 Jim LawsonUpdate cells supported for verilog to FIRRTL conversion. commit | commitdiff | tree
2019-02-13 Clifford WolfFix sign handling of real constants commit | commitdiff | tree
2019-02-12 Eddie HungMissing headers for Xcode? commit | commitdiff | tree
2019-02-12 Eddie HungMerge branch 'read_aiger' of github.com:eddiehung/yosys... commit | commitdiff | tree
2019-02-12 Eddie HungUse module->add{Not,And}Gate() functions commit | commitdiff | tree
2019-02-12 Clifford WolfMerge pull request #802 from whitequark/write_verilog_a... commit | commitdiff | tree
2019-02-12 Clifford WolfMerge pull request #806 from daveshah1/fsm_opt_no_reset commit | commitdiff | tree
2019-02-11 Eddie HungDo not break for constraints commit | commitdiff | tree
2019-02-11 Eddie HungNo increment line_count for binary ANDs commit | commitdiff | tree
2019-02-11 Eddie HungDo not ignore newline after AND in binary AIG commit | commitdiff | tree
2019-02-08 Eddie HungMerge remote-tracking branch 'origin/dff_init' into... commit | commitdiff | tree
2019-02-08 Eddie HungaddDff -> addDffGate as per @daveshah1 commit | commitdiff | tree
2019-02-08 Eddie HungFix tabulation commit | commitdiff | tree
2019-02-08 Eddie Hung-module_name arg to go before -clk_name commit | commitdiff | tree
2019-02-08 Eddie HungSupport and differentiate between ASCII and binary... commit | commitdiff | tree
2019-02-08 Eddie HungAdd missing "[options]" to read_blif help commit | commitdiff | tree
2019-02-08 Eddie HungAllow module name to be determined by argument too commit | commitdiff | tree
2019-02-08 Eddie HungRefactor into AigerReader class commit | commitdiff | tree
2019-02-08 Eddie HungParse binary AIG files commit | commitdiff | tree
2019-02-08 Eddie HungAdd binary AIGs converted from AAG commit | commitdiff | tree
2019-02-08 Eddie HungRefactor to parse_aiger_header() commit | commitdiff | tree
2019-02-08 Eddie HungAdd comment commit | commitdiff | tree
2019-02-08 Eddie HungHandle reset logic in latches commit | commitdiff | tree
2019-02-08 Eddie HungChange literal vars from int to unsigned commit | commitdiff | tree
2019-02-08 Eddie HungCreate clk outside of latch loop commit | commitdiff | tree
2019-02-08 Eddie HungHandle latch symbols too commit | commitdiff | tree
2019-02-08 Eddie HungRemove return after log_error commit | commitdiff | tree
2019-02-08 Eddie HungAdd support for symbol tables commit | commitdiff | tree
2019-02-08 Eddie HungStub for binary AIGER commit | commitdiff | tree
2019-02-07 David Shahfsm_opt: Fix runtime error for FSMs without a reset... commit | commitdiff | tree
2019-02-06 Eddie HungCope WIDTH of ff/latch cells is default of zero commit | commitdiff | tree
2019-02-06 Eddie HungRefactor commit | commitdiff | tree
2019-02-06 Eddie HungRemove check for cell->name[0] == '$' commit | commitdiff | tree
2019-02-06 Eddie HungMerge branch 'dff_init' of https://github.com/eddiehung... commit | commitdiff | tree
2019-02-06 Eddie HungRevert most of autotest.sh; for non *.v use Yosys to... commit | commitdiff | tree
2019-02-06 Eddie HungRefactor commit | commitdiff | tree
2019-02-06 Eddie Hungwrite_verilog to cope with init attr on q when -noexpr commit | commitdiff | tree
2019-02-06 Eddie HungAdd INIT parameter to all ff/latch cells commit | commitdiff | tree
2019-02-06 Eddie HungAdd tests for simple cases using defparam commit | commitdiff | tree
2019-02-06 Eddie HungAdd -B option to autotest.sh to append to backend_opts commit | commitdiff | tree
2019-02-06 Eddie HungExtend testcase commit | commitdiff | tree
2019-02-06 Eddie HungAdd testcase commit | commitdiff | tree
2019-02-06 Eddie HungRename ASCII tests commit | commitdiff | tree
2019-02-06 Eddie HungWIP commit | commitdiff | tree
2019-02-06 Clifford WolfAdd missing blackslash-to-slash convertion to smtio... commit | commitdiff | tree
2019-02-05 Eddie HungAdd tests commit | commitdiff | tree
2019-01-29 whitequarkwrite_verilog: correctly emit asynchronous transparent... commit | commitdiff | tree
2019-01-27 Clifford WolfMerge pull request #798 from mmicko/master commit | commitdiff | tree
2019-01-27 Clifford WolfMerge pull request #800 from whitequark/write_verilog_t... commit | commitdiff | tree
2019-01-27 Clifford WolfMerge branch 'whitequark-write_verilog_keyword' commit | commitdiff | tree
2019-01-27 Clifford WolfRemove asicworld tests for (unsupported) switch-level... commit | commitdiff | tree
2019-01-27 whitequarkwrite_verilog: write $tribuf cell as ternary. commit | commitdiff | tree
2019-01-27 whitequarkwrite_verilog: escape names that match SystemVerilog... commit | commitdiff | tree
2019-01-25 David ShahMerge pull request #796 from whitequark/proc_clean_typo commit | commitdiff | tree
2019-01-25 Miodrag MilanovicFixed Anlogic simulation model commit | commitdiff | tree
2019-01-23 whitequarkproc_clean: fix critical typo. commit | commitdiff | tree
2019-01-19 Clifford WolfMerge pull request #793 from whitequark/proc_clean_fix_... commit | commitdiff | tree
2019-01-18 whitequarkproc_clean: fix fully def check to consider compare... commit | commitdiff | tree
2019-01-17 Clifford WolfCleanups in igloo2 example design commit | commitdiff | tree
2019-01-17 Clifford WolfAdd SF2 IO buffer insertion commit | commitdiff | tree
2019-01-17 Clifford WolfImprove Igloo2 example commit | commitdiff | tree
2019-01-17 Clifford WolfAdd "synth_sf2 -vlog", fix "synth_sf2 -edif" commit | commitdiff | tree
2019-01-17 Clifford WolfAdd "write_edif -gndvccy" commit | commitdiff | tree
2019-01-15 Clifford WolfAdd optional nullstr argument to log_id() commit | commitdiff | tree
2019-01-15 Clifford WolfFix handling of $shiftx in Verilog back-end commit | commitdiff | tree
2019-01-15 Clifford WolfMerge pull request #788 from whitequark/master commit | commitdiff | tree
2019-01-15 Clifford WolfMerge pull request #787 from whitequark/flowmap_relax commit | commitdiff | tree
2019-01-14 whitequarkmanual: document some gates. commit | commitdiff | tree
2019-01-14 whitequarkmanual: explain $tribuf cell. commit | commitdiff | tree
2019-01-08 Clifford WolfImprove igloo2 example commit | commitdiff | tree
2019-01-08 whitequarkflowmap: clean up terminology. commit | commitdiff | tree
2019-01-08 whitequarkflowmap: implement depth relaxation. commit | commitdiff | tree
2019-01-07 Clifford WolfFix typo in manual commit | commitdiff | tree
2019-01-07 Clifford WolfBugfix in $memrd sharing commit | commitdiff | tree
2019-01-07 Clifford WolfMerge pull request #782 from whitequark/flowmap_dfs commit | commitdiff | tree
2019-01-07 Clifford WolfSwitch "bugpoint" from system() to run_command() commit | commitdiff | tree
2019-01-07 Clifford WolfMerge pull request #783 from whitequark/bugpoint commit | commitdiff | tree
2019-01-07 whitequarkbugpoint: new pass. commit | commitdiff | tree
2019-01-06 whitequarkflowmap: construct a max-volume max-flow min-cut, not... commit | commitdiff | tree
2019-01-06 Clifford WolfMerge pull request #780 from phire/rename_from_wire commit | commitdiff | tree
2019-01-06 Scott MansellRename cells based on the wires they drive. commit | commitdiff | tree
2019-01-05 Clifford WolfAdd skeleton Yosys-Libero igloo2 example project commit | commitdiff | tree
2019-01-05 Clifford WolfBugfix in Verilog string handling commit | commitdiff | tree
2019-01-04 whitequarkflowmap: add -minlut option, to allow postprocessing... commit | commitdiff | tree
2019-01-04 Clifford WolfMerge pull request #777 from mmicko/achronix_cell_sim_fix commit | commitdiff | tree
2019-01-04 Miodrag MilanovicFix cells_sim.v for Achronix FPGA commit | commitdiff | tree
2019-01-04 Clifford WolfRemove -m32 Verific eval lib build instructions commit | commitdiff | tree
2019-01-04 Clifford WolfMerge pull request #776 from mmicko/unify_noflatten commit | commitdiff | tree
2019-01-04 Clifford WolfUpdate Verific default path commit | commitdiff | tree
2019-01-04 whitequarkflowmap: cleanup for clarity. NFCI. commit | commitdiff | tree
2019-01-04 Miodrag MilanovicUnify usage of noflatten among architectures commit | commitdiff | tree
2019-01-04 whitequarkflowmap: improve debug graph output. NFC. commit | commitdiff | tree
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