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yosys.git
2019-08-29
Eddie Hung
Add LP timings
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2019-08-29
Eddie Hung
LX -> LP
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2019-08-29
Eddie Hung
Merge remote-tracking branch 'origin/eddie/fix_carry_wr...
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2019-08-29
Eddie Hung
Add run-test.sh too
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2019-08-29
Eddie Hung
Do not overwrite LUT param
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2019-08-29
Eddie Hung
Add SB_CARRY to ice40_opt test
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2019-08-29
Eddie Hung
Add ice40_opt test
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2019-08-29
Eddie Hung
Do not overwrite LUT param
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2019-08-29
Eddie Hung
Add SB_CARRY to ice40_opt test
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2019-08-29
Eddie Hung
Add ice40_opt test
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2019-08-29
Eddie Hung
Revert "Revert "Fix omode which inserts an output if...
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2019-08-29
Eddie Hung
Revert "Output "h" extension only if boxes"
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2019-08-29
Eddie Hung
Merge remote-tracking branch 'origin/eddie/fix_carry_wr...
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2019-08-29
Eddie Hung
Trailing comma
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2019-08-29
Eddie Hung
Adapt to $__ICE40_CARRY_WRAPPER
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2019-08-29
Eddie Hung
Revert "Remove $__ICE40_FULL_ADDER handling from ice40_...
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2019-08-29
Eddie Hung
Add arrival times for HX devices
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2019-08-29
Eddie Hung
Specify ice40 family to cells_sim.v using define
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2019-08-29
Eddie Hung
Merge remote-tracking branch 'origin/eddie/fix_carry_wr...
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2019-08-29
Eddie Hung
Remove $__ICE40_FULL_ADDER handling from ice40_opt...
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2019-08-29
Eddie Hung
Update box size and timings
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2019-08-29
Eddie Hung
Update to new $__ICE40_CARRY_WRAPPER
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2019-08-28
Eddie Hung
Account for D port being a constant
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2019-08-28
Eddie Hung
Merge branch 'eddie/xilinx_srl' into xaig_arrival
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2019-08-28
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_...
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2019-08-28
Eddie Hung
Merge pull request #1334 from YosysHQ/clifford/async2sy...
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2019-08-28
Eddie Hung
No need to replace Q of slice since $shiftx is autoremove-d
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2019-08-28
Eddie Hung
Add (* clkbuf_sink *) to SRLC16E, reorder ports to...
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2019-08-28
Eddie Hung
More cleanup
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2019-08-28
Eddie Hung
More cleanup
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2019-08-28
Eddie Hung
Do not use default_params dict, hardcode default values...
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2019-08-28
Eddie Hung
Add .gitignore
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2019-08-28
Eddie Hung
Use test_pmgen for xilinx_srl
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2019-08-28
Eddie Hung
Always generate if no match
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2019-08-28
Eddie Hung
Rename test_pmgen arg xilinx_srl.{fixed,variable}
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2019-08-28
Eddie Hung
Do not simplemap for variable test
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2019-08-28
Eddie Hung
Add xilinx_srl test
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2019-08-28
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-28
David Shah
Merge pull request #1332 from YosysHQ/dave/ecp5gsr
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2019-08-28
Clifford Wolf
Merge pull request #1335 from YosysHQ/clifford/paramap
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2019-08-28
Clifford Wolf
Fix typo
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2019-08-28
Clifford Wolf
Add "paramap" pass
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2019-08-28
Clifford Wolf
Add $dlatch support to async2sync
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2019-08-27
Clifford Wolf
Merge pull request #1325 from YosysHQ/eddie/sat_init
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2019-08-27
Marcin Kościelnicki
xilinx: Add SRLC16E primitive.
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2019-08-27
Eddie Hung
Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmap
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2019-08-27
Eddie Hung
Ignore all 1'bx in (* init *)
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2019-08-27
Eddie Hung
Revert to using clean
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2019-08-27
Marcin Kościelnicki
improve clkbuf_inhibit propagation upwards through...
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2019-08-27
David Shah
ecp5: Add GSR support
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2019-08-27
Clifford Wolf
Add "make bumpversion"
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2019-08-27
Eddie Hung
Missing close bracket
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2019-08-27
Eddie Hung
Revert "In sat: 'x' in init attr should not override...
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2019-08-27
Eddie Hung
Remove leftover header
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2019-08-27
Eddie Hung
Improve xilinx_srl.fixed generate, add .variable generate
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2019-08-27
Eddie Hung
Account for maxsubcnt overflowing
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2019-08-27
Eddie Hung
Add xilinx_srl_pm.variable to test_pmgen
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2019-08-26
Eddie Hung
Populate generate for xilinx_srl.fixed pattern
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2019-08-26
Eddie Hung
Add xilinx_srl_fixed, fix typos
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2019-08-26
Eddie Hung
Merge branch 'master' into eddie/xilinx_srl
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2019-08-26
Eddie Hung
Improve tests to check that clkbuf is connected to...
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2019-08-26
Eddie Hung
Merge branch 'master' into mwk/xilinx_bufgmap
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2019-08-26
Eddie Hung
Remove dupe in CHANGELOG, missing end quote
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2019-08-26
Clifford Wolf
Merge tag 'yosys-0.9'
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2019-08-26
Clifford Wolf
Yosys 0.9
yosys-0.9
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2019-08-25
Clifford Wolf
Merge pull request #1112 from acw1251/pyosys_sigsig_issue
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2019-08-24
Eddie Hung
Wire with init on FF part, 1'bx on non-FF part
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2019-08-24
Clifford Wolf
Merge pull request #1327 from YosysHQ/clifford/pmgen
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2019-08-24
Eddie Hung
Create new $__XILINX_SHREG_ cell for variable length too
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2019-08-24
Eddie Hung
Do not allow Q of last cell of variable length SRL...
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2019-08-24
Eddie Hung
Also add first.Q to chain_bits since variable length
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2019-08-24
Eddie Hung
Do not enforce !EN_POLARITY on $dffe
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2019-08-24
Eddie Hung
Create new cell for fixed length SRL
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2019-08-24
Eddie Hung
Cleanup FDRE matching
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2019-08-23
Eddie Hung
Add undocumented feature
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2019-08-23
Eddie Hung
Oops don't need a finally block
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2019-08-23
Eddie Hung
Keep track of bits in variable length chain, to check...
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2019-08-23
Eddie Hung
Don't forget $dff has no EN
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2019-08-23
Eddie Hung
Same for variable length
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2019-08-23
Eddie Hung
Filter on en_port for fixed length
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2019-08-23
Eddie Hung
Check clock is consistent
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2019-08-23
Eddie Hung
Fix last_cell.D
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2019-08-23
Eddie Hung
Revert "Add a unique argument to pmgen's nusers()"
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2019-08-23
Eddie Hung
Revert "Fix polarity"
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2019-08-23
Eddie Hung
Fix polarity
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2019-08-23
Eddie Hung
Check for non unique nusers/fanouts
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2019-08-23
Eddie Hung
Add a unique argument to pmgen's nusers()
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2019-08-23
Eddie Hung
Update doc
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2019-08-23
Eddie Hung
Remove (* init *) entry when consumed into SRL
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2019-08-23
Eddie Hung
Merge branch 'xaig_arrival' of github.com:YosysHQ/yosys...
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2019-08-23
Eddie Hung
Cleanup
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2019-08-23
Eddie Hung
Revert to upstream
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2019-08-23
Eddie Hung
Fix spacing
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2019-08-23
Eddie Hung
Remove unused model
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2019-08-23
Eddie Hung
indo -> into
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2019-08-23
Eddie Hung
indo -> into
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2019-08-23
Eddie Hung
Forgot to slice
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2019-08-23
Eddie Hung
Cope with possibility that D could connect to Q on...
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2019-08-23
Eddie Hung
Revert earliest to gcc-4.8, compile iverilog with defau...
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2019-08-23
Eddie Hung
Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbo...
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