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yosys.git
2013-12-04
Clifford Wolf
Replaced RTLIL::Const::str with generic decoder method
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2013-12-04
Clifford Wolf
Fix in sincos testbench gen
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2013-12-04
Clifford Wolf
Added sincos test case
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2013-12-04
Clifford Wolf
Added support for local regs in named blocks
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2013-12-04
Clifford Wolf
Fixed gentb_constant handling in autotest backend
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2013-12-04
Clifford Wolf
More ABC releated Makefile changes
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2013-12-03
Clifford Wolf
Minor improvements in ABc build
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2013-12-02
Clifford Wolf
Progress on AppNote 011
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2013-12-02
Clifford Wolf
Fixed submod for non-primitive cells
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2013-12-02
Clifford Wolf
Fixed submod for non-cleaned designs
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2013-12-02
Clifford Wolf
Added Pass:call_newsel API
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2013-12-02
Clifford Wolf
Added "history" command
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2013-12-01
Clifford Wolf
A fix in memory_dff for write ports with static addresses
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2013-12-01
Clifford Wolf
Progress on AppNote 011
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2013-11-29
Clifford Wolf
Progress on AppNote 011
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2013-11-29
Clifford Wolf
Progress on AppNote 011
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2013-11-29
Clifford Wolf
Using RTLIL::id2cstr for prompt printing
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2013-11-29
Clifford Wolf
Added dump -m and -n options
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2013-11-28
Clifford Wolf
Progress on AppNote 011
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2013-11-28
Clifford Wolf
Merge pull request #17 from mschmoelzer/master
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2013-11-28
Clifford Wolf
Fixed temp net name generation in rtlil process generat...
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2013-11-28
Clifford Wolf
Added pattern support to "ls" command
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2013-11-28
Clifford Wolf
Improved ID matching scheme in select (and thus for...
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2013-11-28
Clifford Wolf
Fixes and improvements in "show" command
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2013-11-28
Martin Schmölzer
Include unistd.h in svgview.cpp (required for getcwd...
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2013-11-28
Clifford Wolf
More progress on AppNote 011
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2013-11-28
Clifford Wolf
Added "src" attribute to processes
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2013-11-28
Clifford Wolf
Started writing appnote 011
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2013-11-28
Clifford Wolf
Added support for "show -pause" and "show -format dot"
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2013-11-28
Clifford Wolf
Added QGraphicsWebView to yosys-svgviewer
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2013-11-27
Clifford Wolf
Updated ABC to 9241719523f6
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2013-11-27
Clifford Wolf
Added some svgviewer code for possible future switch...
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2013-11-27
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-11-27
Clifford Wolf
Tighter integration of ABC build
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2013-11-27
Clifford Wolf
Set version number to 0.1.0+
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2013-11-25
Clifford Wolf
Started implementing undef support in "sat" command
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2013-11-25
Clifford Wolf
Bugfixes in new "stat" command
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2013-11-25
Clifford Wolf
Added "stat" command
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2013-11-25
Clifford Wolf
Improvements in satgen undef handling
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2013-11-25
Clifford Wolf
Improvements in satgen undef handling
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2013-11-25
Clifford Wolf
Added ezsat vec_const() api
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2013-11-25
Clifford Wolf
Started implementing undef handling in satgen
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2013-11-25
Clifford Wolf
Removed undef feature from ezsat api
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2013-11-24
Clifford Wolf
Using simplemap mappers from techmap
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2013-11-24
Clifford Wolf
Added simplemap pass
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2013-11-24
Clifford Wolf
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
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2013-11-24
Clifford Wolf
Added module->avail_parameters (for advanced techmap...
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2013-11-24
Clifford Wolf
Added techmap -D and -I options
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2013-11-24
Clifford Wolf
Added verilog frontend -ignore_redef option
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2013-11-24
Clifford Wolf
Added "techmap -share_map" option
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2013-11-24
Clifford Wolf
Early wire/reg/parameter width calculation in ast/simplify
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2013-11-24
Clifford Wolf
Updated TODOs
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2013-11-24
Clifford Wolf
Fixed xilinx/example_sim_counter test bench
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2013-11-24
Clifford Wolf
Added proper dumping of signed/unsigned parameters...
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2013-11-24
Clifford Wolf
Added support for signed parameters in ilang
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2013-11-24
Clifford Wolf
Removed now obsolete test cases
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2013-11-24
Clifford Wolf
Remove auto_wire framework (smarter than the verilog...
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2013-11-24
Clifford Wolf
Implemented correct handling of signed module parameters
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2013-11-24
Clifford Wolf
Added modelsim support to autotest
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2013-11-24
Clifford Wolf
Fixed "flatten" top-module detection: Only use on fully...
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2013-11-24
Clifford Wolf
Fixed "make install" dependencies
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2013-11-24
Clifford Wolf
Added "top" attribute to mark top module in hierarchy
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2013-11-23
Clifford Wolf
Updated command-reference-manual.tex
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2013-11-23
Clifford Wolf
AppNote 010 typo fixes and corrections
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2013-11-23
Clifford Wolf
AppNote 010 progress
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2013-11-23
Clifford Wolf
Improved handling of techmap special wires
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2013-11-23
Clifford Wolf
Improved handling of initialized registers
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2013-11-23
Clifford Wolf
Added more generic _TECHMAP_ wire mechanism to techmap...
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2013-11-23
Clifford Wolf
Making prograss on Appnote 010
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2013-11-22
Clifford Wolf
Progress on AppNote 010
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2013-11-22
Clifford Wolf
Started to write on AppNote 010: Verilog to BLIF
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2013-11-22
Clifford Wolf
Updated command-reference-manual.tex
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2013-11-22
Clifford Wolf
Renamed "placeholder" to "blackbox"
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2013-11-22
Clifford Wolf
Some driver changes/fixes
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2013-11-22
Clifford Wolf
Fixed O(n^2) performance bug in verilog preprocessor
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2013-11-22
Clifford Wolf
Added more performance measurement infrastructure
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2013-11-22
Clifford Wolf
Enable {* .. *} feature per default (removes dependency...
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2013-11-22
Clifford Wolf
Massive performance improvement from refactoring RTLIL...
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2013-11-22
Clifford Wolf
Added SigBit struct and refactored RTLIL::SigSpec:...
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2013-11-22
Clifford Wolf
Improved make rules for profiling and debugging
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2013-11-21
Clifford Wolf
Updated abc
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2013-11-21
Clifford Wolf
Implemented $_DFFSR_ expression generator in verilog...
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2013-11-21
Clifford Wolf
Fixed async proc detection in mem2reg
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2013-11-21
Clifford Wolf
Major improvements in mem2reg and added "init" sync...
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2013-11-21
Clifford Wolf
Fixed a bug in "add -global_input"
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2013-11-20
Clifford Wolf
Added "proc_arst -global_arst" feature
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2013-11-20
Clifford Wolf
Fixed ilang parser: memory width
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2013-11-20
Clifford Wolf
Added "add" command (only wires for now)
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2013-11-20
Clifford Wolf
Another name resolution bugfix for generate blocks
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2013-11-20
Clifford Wolf
Implemented indexed part selects
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2013-11-20
Clifford Wolf
Do not allow memory bit select on the left side of...
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2013-11-20
Clifford Wolf
Added "synthesis" in (synopsys|synthesis) comment support
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2013-11-20
Clifford Wolf
Fixed name resolution of local tasks and functions...
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2013-11-20
Clifford Wolf
Implemented part/bit select on memory read
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2013-11-20
Clifford Wolf
Updated TODOs in README file
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2013-11-20
Clifford Wolf
Added init= attribute for fpga-style reset values
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2013-11-19
Clifford Wolf
Added "make config-sudo"
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2013-11-19
Clifford Wolf
Install simlib in datdir
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2013-11-19
Clifford Wolf
Large improvements in yosys-config
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2013-11-19
Clifford Wolf
Fixed parsing of module arguments when one type is...
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