riscv-isa-sim.git
2011-05-19 Yunsup Lee[sim] change default hwvl
2011-05-19 Yunsup Lee[sim] vlen calc reflects the hardware
2011-05-18 Andrew Waterman[sim] fixed fcvt rounding bugs
2011-05-18 Yunsup Lee[opcodes,pk,sim] add more vector traps (for #banks...
2011-05-16 Andrew Waterman[sim,pk] cleanups & initial virtual memory support
2011-05-16 Yunsup Lee[sim,xcc] change cond. mov inst format, add implementation
2011-05-16 Yunsup Lee[opcodes,pk,sim,xcc] resolve a conflict
2011-05-16 Yunsup Lee[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec...
2011-05-14 Andrew Waterman[sim] initial support for virtual memory
2011-05-14 Andrew Waterman[sim] stubs for perfctr instructions
2011-05-13 Andrew Watermantweaked encoding of rdcycle & cousins
2011-05-06 Andrew Waterman[sim] fixed building sim without cache simulators
2011-05-01 Andrew Waterman[sim] hacked in a dcache simulator
2011-04-25 Andrew Waterman[xcc,sim,opcodes] added c.addiw
2011-04-24 Andrew Waterman[xcc,sim,opcodes] added more RVC instructions
2011-04-24 Andrew Waterman[sim] fixed divw/remw crashing simulator
2011-04-19 Andrew Waterman[xcc,sim] rv64 'w' instruction semantics changed
2011-04-19 Andrew Waterman[xcc,sim,opcodes] added rvc conditional branches
2011-04-17 Andrew Waterman[sim] removed undefined behavior for non-canonical...
2011-04-17 Andrew Waterman[sim] added "str" debug command
2011-04-15 Andrew Waterman[sim] fixed jalr immediate bug
2011-04-15 Andrew Waterman[sim] added icache simulator (disabled by default)
2011-04-13 Andrew Waterman[xcc,pk,sim] added privileged cflush instruction
2011-04-13 Andrew Waterman[xcc,sim] fixed RM field
2011-04-12 Andrew Waterman[xcc,sim] rvc loads and stores
2011-04-12 Andrew Waterman[sim,pk] fixed minor pk bugs and trap codes
2011-04-12 Andrew Waterman[sim] fixed FSR exception field bug
2011-04-12 Andrew Waterman[xcc,sim,opcodes] more rvc instructions and bug fixes
2011-04-10 Yunsup Lee[sim] add disable option for vector
2011-04-10 Yunsup Lee[sim] set SR_EV for uts
2011-04-10 Yunsup Lee[sim] add vector traps to vector instructions
2011-04-10 Yunsup Lee[sim] add vt stuff
2011-04-10 Andrew Waterman[xcc, sim] added rvc insn c.li; misc fixes
2011-04-10 Andrew Waterman[sim,pk] reorganized status register
2011-04-10 Andrew Waterman[xcc,pk,sim,opcodes] added first RVC instruction
2011-04-08 Andrew Waterman[sim] fixed multiply-high in rv32
2011-04-07 Andrew Waterman[pk,sim] fixed parse-opcodes bug
2011-04-07 Yunsup Lee[opcodes,pk,sim,xcc] fix utidx - add rd
2011-04-05 Yunsup Lee[opcodes,pk,sim,xcc] fix vector mem instruction format...
2011-04-04 Yunsup Lee[opcodes,pk,sim,xcc] add leftover vector instructions...
2011-04-04 Yunsup Lee[opcodes,pk,sim,xcc] add vector mem instructions
2011-04-04 Yunsup Lee[opcodes,pk,sim,xcc] add stop,utidx instructions
2011-04-04 Yunsup Lee[opcodes,pk,sim,xcc] add fence instructions for vector...
2011-03-30 Andrew Waterman[xcc] fixed bug in amo{maxu,minu}.w
2011-03-26 Andrew Waterman[opcodes] minor opcode changes
2011-03-26 Andrew Waterman[sim,pk,xcc,opcodes] removed fminmag/fmaxmag
2011-03-25 Andrew Waterman[xcc,pk,opcodes,sim] updated encoding/insn names
2011-03-18 Andrew Waterman[sim] LWU now illegal in RV32
2011-03-01 Andrew Waterman[xcc,sim] branches are pc-relative (not pc+4) again
2011-02-15 Andrew Waterman[xcc,opcodes,pk,sim] krste's re-renaming spree
2011-02-15 Andrew Waterman[xcc,sim,opcodes] removed mtflh/mffl/mffh
2011-02-05 Andrew Waterman[sim,pk] added interrupt-pending field to cause reg
2011-02-02 Andrew Waterman[sim,xcc,opcodes] added back mtflh.d
2011-02-02 Andrew Waterman[opcodes,pk,sim,xcc] synci now bombs whole icache
2011-02-02 Andrew Waterman[xcc,opcodes,pk,sim] cleanup to FP ISA
2011-02-02 Andrew Waterman[sim] added nearest/ties to max magnitude rounding...
2011-01-27 Andrew Waterman[sim] changed divide-by-0 semantics
2011-01-26 Andrew Waterman[sim,opcodes] add mulhsu instruction
2011-01-26 Andrew Waterman[opcodes,pk,sim,xcc] great renumbering of 2011, part...
2011-01-21 Andrew Waterman[sim, pk, xcc, opcodes] great instruction renaming...
2011-01-19 Andrew Waterman[opcodes, sim, xcc] made *w insns illegal in RV32
2011-01-17 Andrew Waterman[opcodes, pk, sim, xcc] removed nor, normalized macros...
2011-01-12 Andrew Waterman[sim] fix jalr bug
2011-01-04 Yunsup Lee[opcodes,pk,sim,xcc] flip fields to favor little endian
2010-12-27 Andrew Waterman[sim] fixed some compiler warnings
2010-12-27 Andrew Waterman[sim] cleaned up handling of link register
2010-11-22 Andrew Waterman[sim] handle integer division overflow
2010-11-22 Andrew Waterman[opcodes, pk, sim, xcc] Tweaked FP encoding
2010-11-22 Andrew Waterman[opcodes] generate latex and verilog correctly
2010-11-22 Andrew Waterman[pk] various PK cleanups/speedups
2010-11-22 Andrew Waterman[xcc, sim, pk, opcodes] new instruction encoding!
2010-11-22 Andrew Waterman[xcc, sim, pk] link register is now x1
2010-11-22 Andrew Waterman[opcodes, pk, sim, xcc] made jumps shorter and PC-relative
2010-10-26 Andrew Waterman[sim] removed unnecessary trap in mfcr instruction
2010-10-26 Andrew Waterman[sim,xcc] fixed minor bugs related to tp/cr29
2010-10-26 Yunsup Lee[pk,sim,xcc] get rid of at register, introduce tp register
2010-10-26 Andrew Waterman[sim,xcc,pk,opcodes] static rounding modes for FP insns
2010-10-16 Andrew Waterman[pk, sim] added FPU emulation support to proxy kernel
2010-10-15 Andrew Waterman[sim] made softfloat files C instead of C++
2010-10-12 Andrew Waterman[sim] added writeback tracing
2010-10-07 Andrew Waterman[xcc] modified opcodes for better FP decode mapping
2010-10-06 Andrew Waterman[opcodes] added code field back to syscall/break
2010-10-06 Andrew Waterman[xcc] removed CEXC field from FSR
2010-10-05 Andrew Waterman[xcc,sim] eliminated vectored traps
2010-10-03 Andrew Waterman[sim, xcc] changed cvt/trunc to use GPRs for int args
2010-10-03 Andrew Waterman[xcc, sim] mff now uses rs2 for data
2010-09-29 Andrew Waterman[opcodes, sim, xcc] added mffl.d instruction
2010-09-23 Andrew Waterman[xcc, sim] eliminated zero-extended immediates
2010-09-22 Andrew Waterman[sim] fixed bug in which shift operands were reversed
2010-09-21 Andrew Waterman[xcc, sim] changed instruction format so imm12 subs...
2010-09-14 Andrew Waterman[xcc, sim] replaced ble/bleu with bge/bgeu
2010-09-13 Andrew Waterman[sim] renamed sllv to sll (same for other shifts)
2010-09-13 Andrew Waterman[xcc, sim] moved shamt field and renamed shifts
2010-09-13 Andrew Waterman[xcc, sim] branches now are next-PC-based, not PC-based
2010-09-11 Andrew Waterman[xcc] fixed broken 32-bit FP ABI
2010-09-11 Andrew Waterman[sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bit
2010-09-11 Andrew Waterman[sim, pk] cleaned up exception vectors and FP exc flags
2010-09-11 Yunsup Lee[opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit)
2010-09-10 Yunsup Lee[opcodes,sim,xcc] move opcodes for 3 source instructions
2010-09-10 Andrew WatermanRevert "[xcc, sim] added slei/sleui in lieu of slti...
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