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yosys.git
2015-08-16
Clifford Wolf
Another bugfix for ice40 and xilinx brams_init make...
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2015-08-16
Clifford Wolf
Fixed Makefile rules for generated share files
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2015-08-16
Clifford Wolf
Added $tribuf and $_TBUF_ sim models
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2015-08-16
Clifford Wolf
Added tribuf command
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2015-08-16
Clifford Wolf
Added $tribuf and $_TBUF_ cell types
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2015-08-16
Clifford Wolf
Fixed opt_clean handling of inout ports
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2015-08-15
Clifford Wolf
Fixed generation of smt2 concat statements
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2015-08-14
Larry Doolittle
Fix version strings for out-of-tree builds
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2015-08-14
Larry Doolittle
Another block of spelling fixes
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2015-08-14
Larry Doolittle
Keep gcc from complaining about uninitialized variables
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2015-08-14
Clifford Wolf
Re-created command-reference-manual.tex, copied some...
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2015-08-14
Clifford Wolf
Spell check (by Larry Doolittle)
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2015-08-13
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-08-13
Clifford Wolf
More ASCII encoding fixes
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2015-08-13
Clifford Wolf
Fixed CRLF line endings
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2015-08-13
Clifford Wolf
Some ASCII encoding fixes (comments and docs) by Larry...
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2015-08-12
Clifford Wolf
Added "write_smt2 -regs"
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2015-08-12
Clifford Wolf
Fixed "make clean" for out-of-tree builds
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2015-08-12
Clifford Wolf
Adjust makefiles to work with out-of-tree builds
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2015-08-12
Clifford Wolf
Improved handling of "keep" attributes in hierarchical...
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2015-08-12
Clifford Wolf
Fixed hashlib for 64 bit int keys
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2015-08-12
Clifford Wolf
Added SMV back-end 'test_cells.sh' script
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2015-08-12
Clifford Wolf
Merge pull request #70 from gaomy3832/bugfix
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2015-08-11
Mingyu Gao
Remove unused blackbox modules in opt_clean.
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2015-08-11
Mingyu Gao
Bugfix for cell hash cache option in opt_share.
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2015-08-11
Clifford Wolf
Fixed handling of [a-fxz?] in decimal constants
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2015-08-11
Clifford Wolf
Added missing ct_all setup to opt_clean
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2015-08-10
Mingyu Gao
Bugfix for cell hash cache option in opt_share.
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2015-08-09
Clifford Wolf
Use MEMID as name for $mem cell
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2015-08-06
Clifford Wolf
Merge pull request #69 from zeldin/master
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2015-08-06
Marcus Comstedt
Added iCE40 WARMBOOT cell
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2015-08-05
Clifford Wolf
Remove some very strange whitespace in btor.cc (by...
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2015-08-05
Clifford Wolf
Bugfix in SMV back-end for partially unassigned wires
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2015-08-04
Clifford Wolf
Added ENABLE_LIBYOSYS Makefile option
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2015-08-04
Clifford Wolf
Added $assert support to SMV back-end
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2015-08-04
Clifford Wolf
Added libyosys.so build
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2015-08-01
Clifford Wolf
Merge pull request #68 from zeldin/master
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2015-08-01
Marcus Comstedt
Add -noautowire option to verilog frontend
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2015-07-31
Clifford Wolf
Added WORDS parameter to $meminit
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2015-07-30
Clifford Wolf
Fixed flatten $meminit handling
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2015-07-29
Clifford Wolf
Improvements in BLIF back-end
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2015-07-29
Clifford Wolf
Fixed nested mem2reg
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2015-07-27
Clifford Wolf
Don't write a 17th memory bit in ice40/cells_sim (by...
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2015-07-27
Clifford Wolf
Fixed "check" command for inout ports
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2015-07-25
Clifford Wolf
Some cleanups in opt_rmdff
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2015-07-25
Clifford Wolf
Added "miter -assert"
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2015-07-25
Clifford Wolf
Keep modules with $assume (like $assert)
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2015-07-24
Clifford Wolf
Improved $adff simplification
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2015-07-20
Clifford Wolf
iCE40 DFF sim models: init Q regs to 0
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2015-07-18
Clifford Wolf
Fixed techmap processes error msg
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2015-07-18
Clifford Wolf
Avoid tristate warning for blackbox ice40/cells_sim.v
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2015-07-16
Clifford Wolf
Some fixes in "select" command
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2015-07-10
Clifford Wolf
Fixed YosysJS.create_worker() usage of this.url_prefix
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2015-07-06
Clifford Wolf
Improved liberty file test case
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2015-07-06
Clifford Wolf
Updated ABC
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2015-07-06
Clifford Wolf
Do not collect disabled $memwr cells
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2015-07-04
Clifford Wolf
Improved YosysJS WebWorker API
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2015-07-03
Clifford Wolf
Bugfix in fsm_extract
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2015-07-02
Clifford Wolf
Added "synth -nofsm"
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-07-01
Clifford Wolf
Added opt_const -clkinv
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2015-06-30
Clifford Wolf
Added logic-loop error handling to freduce
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2015-06-29
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-06-29
Clifford Wolf
Bugfix in chparam
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2015-06-29
Clifford Wolf
Added design->rename(module, new_name)
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2015-06-28
Clifford Wolf
Added YosysJS.create_worker()
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2015-06-20
Clifford Wolf
iCE40: set min bram efficiency to 2%
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2015-06-20
Clifford Wolf
Using static mem size of 128 MB in emcc build
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2015-06-19
Clifford Wolf
Added init support to SMV back-end
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2015-06-19
Clifford Wolf
Progress in SMV back-end
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2015-06-19
Clifford Wolf
Progress in SMV back-end
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2015-06-18
Clifford Wolf
Progress in SMV back-end
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2015-06-17
Clifford Wolf
Progress in SMV back-end
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2015-06-17
Clifford Wolf
Added "rename -top new_name"
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2015-06-17
Clifford Wolf
Progress in SMV back-end
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2015-06-16
Clifford Wolf
Progress in SMV back-end
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2015-06-15
Clifford Wolf
Added "synth -nordff -noalumacc"
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2015-06-15
Clifford Wolf
Progress in SMV back-end
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2015-06-15
Clifford Wolf
Progress in SMV back-end
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2015-06-14
Clifford Wolf
Added "write_smv" skeleton
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2015-06-14
Clifford Wolf
Removed debug code from write_smt2
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2015-06-14
Clifford Wolf
Modernized memory_dff (and fixed a bug)
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2015-06-14
Clifford Wolf
Added "memory -nordff"
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2015-06-14
Clifford Wolf
Added write_smt2 -mem
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2015-06-11
Clifford Wolf
Makefile fix for YosysJS build
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2015-06-11
Clifford Wolf
Fixed cstr_buf for std::string with small string optimi...
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2015-06-11
Clifford Wolf
Improvements in cellaigs.cc and "json -aig"
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2015-06-10
Clifford Wolf
AigMaker refactoring
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2015-06-10
Clifford Wolf
Added "json -aig"
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2015-06-10
Clifford Wolf
Renamed "aig" to "aigmap"
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2015-06-10
Clifford Wolf
Fixed cellaigs port extending
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2015-06-09
Clifford Wolf
Added "aig" pass
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2015-06-09
Clifford Wolf
synth_ice40 now flattens by default
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2015-06-09
Clifford Wolf
Added cellaigs API
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2015-06-09
Clifford Wolf
Merge clock inverters in memory_dff
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2015-06-09
Clifford Wolf
Merge branch 'verilog-backend-memV2' of github.com...
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2015-06-08
luke whittlesey
$mem cell in verilog backend : grouped writes by clock
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2015-06-08
Clifford Wolf
Fixed "avail_parameters" handling in module clone/copy
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2015-06-08
Clifford Wolf
Added log_dump() support for IdStrings
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2015-06-08
Clifford Wolf
Fixed handling of parameters with reversed range
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