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yosys.git
2014-03-13 Siesh1oo - Makefile: include $(PWD) in PATH, since 'make test... commit | commitdiff | tree
2014-03-13 Siesh1oo - Makefile: export PATH=${DESTDIR}/bin:$(PATH) and... commit | commitdiff | tree
2014-03-13 Siesh1oo - kernel/register.h, kernel/driver.cc: refactor rewrit... commit | commitdiff | tree
2014-03-13 Siesh1oo - Makefile: don't export DYLD_LIBRARY_PATH/LD_LIBRARY_... commit | commitdiff | tree
2014-03-13 Siesh1oo - .gitignore: ignore qmake/OSX package libs/svgviewer... commit | commitdiff | tree
2014-03-13 Siesh1oo - Makefile: include $(PWD) in PATH, since 'make test... commit | commitdiff | tree
2014-03-13 Siesh1oo - Makefile: fix typo in LDFLAGS: obviously -L, not... commit | commitdiff | tree
2014-03-13 Siesh1oo - Makefile: export PATH=${DESTDIR}/bin:$(PATH) and... commit | commitdiff | tree
2014-03-13 Siesh1oo - Makefile: resolve merge conflict. commit | commitdiff | tree
2014-03-12 Clifford WolfSome fixes in libs/minisat (thanks to Siesh1oo) commit | commitdiff | tree
2014-03-12 Siesh1oo - kernel/register.h, kernel/driver.cc: refactor rewrit... commit | commitdiff | tree
2014-03-12 Clifford WolfFixed dependencies of "make test" commit | commitdiff | tree
2014-03-12 Clifford WolfAdded libs/minisat (copy of minisat git master) commit | commitdiff | tree
2014-03-11 Clifford WolfOSX compatible creation of stdcells.inc, using code... commit | commitdiff | tree
2014-03-11 Clifford WolfMerged addition of SED makefile variable from github... commit | commitdiff | tree
2014-03-11 Clifford WolfMerged a few fixes for non-posix systems from github... commit | commitdiff | tree
2014-03-11 Clifford WolfAdded support for `line compiler directive commit | commitdiff | tree
2014-03-11 Clifford WolfFixed memory corruption in passes/abc/blifparse.cc commit | commitdiff | tree
2014-03-11 Clifford WolfFixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh commit | commitdiff | tree
2014-03-11 Clifford WolfUse "verilog -noattr" in tests/techmap/mem_simple_4x1... commit | commitdiff | tree
2014-03-10 Clifford WolfFixed a typo in RTLIL::Module::addReduce... commit | commitdiff | tree
2014-03-10 Clifford WolfImproved verific command (added support for some operators) commit | commitdiff | tree
2014-03-10 Clifford WolfImprovements in verific command commit | commitdiff | tree
2014-03-10 Clifford WolfAdded RTLIL::Module::add... helper methods commit | commitdiff | tree
2014-03-09 Clifford WolfAdded "verific" command commit | commitdiff | tree
2014-03-09 Clifford WolfFixed dumping of timing() { .. } block in libparse commit | commitdiff | tree
2014-03-09 Clifford WolfVerbose reading of liberty and constr files in ABC... commit | commitdiff | tree
2014-03-07 Clifford WolfFixed bug in freduce command commit | commitdiff | tree
2014-03-07 Clifford WolfSome minor code cleanups in freduce command commit | commitdiff | tree
2014-03-07 Clifford WolfBugfix in ilang frontend autoidx recovery commit | commitdiff | tree
2014-03-07 Clifford WolfUse log_abort() and log_assert() in BTOR backend commit | commitdiff | tree
2014-03-06 Clifford WolfAdded freduce -dump commit | commitdiff | tree
2014-03-06 Clifford WolfAdded freduce -stop commit | commitdiff | tree
2014-03-06 Clifford WolfFixed gcc compiler warning commit | commitdiff | tree
2014-03-06 Clifford WolfFixed undef handling in opt_reduce commit | commitdiff | tree
2014-03-06 Clifford WolfFixes for improved techmap of shifts with large B inputs commit | commitdiff | tree
2014-03-06 Clifford WolfFixed use of frozen literals in SatGen commit | commitdiff | tree
2014-03-06 Clifford WolfStrictly zero-extend unsigned A-inputs of shift operati... commit | commitdiff | tree
2014-03-06 Clifford WolfAdded techmap -max_iter option commit | commitdiff | tree
2014-03-06 Clifford WolfImproved techmap of shift with wide B inputs commit | commitdiff | tree
2014-03-06 Clifford WolfStrictly zero-extend unsigned A-inputs of shift operations commit | commitdiff | tree
2014-03-05 Clifford WolfSwitched to EZMINISAT_SIMPSOLVER as default SAT solver commit | commitdiff | tree
2014-03-05 Clifford WolfInclude id2ast pointers when dumping AST commit | commitdiff | tree
2014-03-05 Clifford WolfFixed merging of compatible wire decls in AST frontend commit | commitdiff | tree
2014-03-05 Clifford WolfBugfix in recursive AST simplification commit | commitdiff | tree
2014-03-03 Clifford Wolffixed freduce for Minisat::SimpSolver: use frozen_literal() commit | commitdiff | tree
2014-03-03 Clifford WolfezSAT: Added frozen_literal() API commit | commitdiff | tree
2014-03-03 Clifford WolfezSAT: Fixed handling of eliminated Literals, added... commit | commitdiff | tree
2014-03-01 Clifford WolfAdded ezSAT::eliminated API to help the SAT solver... commit | commitdiff | tree
2014-03-01 Clifford WolfezSAT bugfix: don't call virtual methods in base class... commit | commitdiff | tree
2014-03-01 Clifford WolfRemoved ezSAT::assumed() API commit | commitdiff | tree
2014-03-01 Clifford WolfRemoved ezSAT built-in brute-froce solver commit | commitdiff | tree
2014-03-01 Clifford WolfFixed vhdl2verilog temp dir name commit | commitdiff | tree
2014-03-01 Clifford WolfFixed vhdl2verilog help message commit | commitdiff | tree
2014-02-27 Clifford WolfFixed const folding of $bu0 cells commit | commitdiff | tree
2014-02-26 Clifford WolfFixed bit-extending in $mux argument (use $bu0 instead... commit | commitdiff | tree
2014-02-26 Clifford WolfAdded support for $bu0 to SatGen commit | commitdiff | tree
2014-02-24 Clifford WolfDon't blow up constants unneccessarily in Verilog frontend commit | commitdiff | tree
2014-02-23 Clifford WolfAdded support for Minisat::SimpSolver + ezSAT frezze... commit | commitdiff | tree
2014-02-23 Clifford WolfFixed small memory leak in Pass::call() commit | commitdiff | tree
2014-02-22 Clifford WolfFixed bug in generation of undefs for $memwr MUXes commit | commitdiff | tree
2014-02-22 Clifford WolfFixed bug (typo) in passes/opt/opt_const.cc commit | commitdiff | tree
2014-02-22 Clifford WolfAdded $lut support to blif backend (by user eddiehung... commit | commitdiff | tree
2014-02-22 Clifford WolfAdded ezMiniSat EZMINISAT_INCREMENTAL compile-time... commit | commitdiff | tree
2014-02-22 Clifford WolfMade MiniSat solver backend configurable in ezminisat.h commit | commitdiff | tree
2014-02-21 Clifford WolfAdded workaround for vhdl-style edge triggers from... commit | commitdiff | tree
2014-02-21 Clifford WolfAdded vhdl2verilog commit | commitdiff | tree
2014-02-21 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-21 Clifford WolfBetter handling of nameDef and nameRef in edif backend commit | commitdiff | tree
2014-02-21 Clifford WolfFixed instantiating multi-bit ports in edif backend commit | commitdiff | tree
2014-02-21 Clifford WolfUse private namespace in mem_simple_4x1_map commit | commitdiff | tree
2014-02-21 Clifford WolfAdded tests/techmap/mem_simple_4x1 commit | commitdiff | tree
2014-02-21 Clifford WolfRenamed "write_blif -subckt" to "write_blif -icells... commit | commitdiff | tree
2014-02-21 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-20 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-20 Clifford WolfAdded _TECHMAP_REPLACE_ feature to techmap commit | commitdiff | tree
2014-02-20 Clifford WolfAdded "extract -ignore_parameters" and "extract -ignore... commit | commitdiff | tree
2014-02-20 Clifford WolfAdded "extract -map %<design_name>" commit | commitdiff | tree
2014-02-20 Clifford WolfAdded "design -push" and "design -pop" commit | commitdiff | tree
2014-02-20 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-20 Clifford WolfAdded connwrappers command commit | commitdiff | tree
2014-02-20 Clifford WolfCleanups in handling of read_verilog -defer and -icells commit | commitdiff | tree
2014-02-20 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-19 Clifford WolfAdded vcd2txt.pl and txt2tikztiming.py (tests/tools... commit | commitdiff | tree
2014-02-18 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys commit | commitdiff | tree
2014-02-18 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-18 Clifford WolfAdded techmap support for _TECHMAP_CONNMAP_*_ commit | commitdiff | tree
2014-02-18 Clifford WolfAdded "sat -dump_cnf" commit | commitdiff | tree
2014-02-18 Clifford WolfCoding style corrections in SatHelper::dump_model_to_vcd() commit | commitdiff | tree
2014-02-18 Clifford WolfImproved non-verbose ezSAT::printDIMACS() format commit | commitdiff | tree
2014-02-18 Clifford WolfAdded "sat -initsteps" commit | commitdiff | tree
2014-02-17 Clifford WolfAdded Verilog support for "`default_nettype none" commit | commitdiff | tree
2014-02-17 Clifford WolfRenamed "sat -dump_fail_to_vcd" to "sat -dump_vcd"... commit | commitdiff | tree
2014-02-17 Andrew ZonenbergAdded "-dump_fail_to_vcd" argument to SAT solver commit | commitdiff | tree
2014-02-17 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-17 Clifford WolfBetter preserve wires when flattening (in comparison... commit | commitdiff | tree
2014-02-16 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-16 Clifford WolfAdded some additional checks to techmap commit | commitdiff | tree
2014-02-16 Clifford WolfAdded CONSTMSK and CONSTVAL feature to techmap commit | commitdiff | tree
2014-02-16 Clifford WolfFixed handling of "keep" attribute on wires in opt_clean commit | commitdiff | tree
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