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yosys.git
2019-11-27
Eddie Hung
Promote output wires in sigmap so that can be detected
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2019-11-27
Eddie Hung
Fix wire width
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2019-11-27
Eddie Hung
Fix submod -hidden
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2019-11-27
Eddie Hung
Add -hidden option to submod
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2019-11-26
Eddie Hung
Update docs with bullet points
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2019-11-26
Eddie Hung
Move \init from source wire to submod if output port
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2019-11-26
Eddie Hung
Add testcase where \init is copied
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2019-11-23
Eddie Hung
Remove redundant flatten
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2019-11-23
Eddie Hung
submod to bitty rather bussy, for bussy wires used...
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2019-11-23
Eddie Hung
Stray dump
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2019-11-23
Eddie Hung
Constant driven signals are also an input to submodules
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2019-11-23
Eddie Hung
Add another test with constant driver
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2019-11-23
Eddie Hung
Oops
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2019-11-23
Eddie Hung
Cleanup spacing
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2019-11-23
Eddie Hung
sigmap(wire) should inherit port_output status of POs
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2019-11-23
Eddie Hung
Add testcase
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2019-11-22
Clifford Wolf
Merge pull request #1517 from YosysHQ/clifford/optmem
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2019-11-22
Clifford Wolf
Merge pull request #1515 from YosysHQ/clifford/svastuff
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2019-11-22
Clifford Wolf
Add "opt_mem" pass
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2019-11-22
Clifford Wolf
Add Verific support for SVA nexttime properties
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2019-11-22
Clifford Wolf
Improve handling of verific primitives in "verific...
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2019-11-22
Clifford Wolf
Add Verific SVA support for "always" properties
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2019-11-22
Clifford Wolf
Merge pull request #1511 from YosysHQ/dave/always
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2019-11-22
Marcin Kościelnicki
gowin: Remove show command from tests.
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2019-11-22
Marcin Kościelnicki
gowin: Add missing .gitignore entries
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2019-11-22
David Shah
Update CHANGELOG and README
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2019-11-21
David Shah
sv: Add tests for SV always types
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2019-11-21
David Shah
proc_dlatch: Add error handling for incorrect always_...
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2019-11-21
David Shah
sv: Correct parsing of always_comb, always_ff and alway...
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2019-11-20
Clifford Wolf
Merge pull request #1507 from YosysHQ/clifford/verificfixes
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2019-11-20
Clifford Wolf
Correctly treat empty modules as blackboxes in Verific
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2019-11-20
Clifford Wolf
Do not rename VHDL entities to "entity(impl)" when...
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2019-11-19
Clifford Wolf
Merge pull request #1449 from pepijndevos/gowin
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2019-11-19
Pepijn de Vos
Remove dff init altogether
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2019-11-19
Marcin Kościelnicki
Fix #1462, #1480.
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2019-11-19
Marcin Kościelnicki
xilinx: Add simulation models for MULT18X18* and DSP48A*.
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2019-11-18
Pepijn de Vos
add help for nowidelut and abc9 options
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2019-11-18
Clifford Wolf
Merge pull request #1497 from YosysHQ/mwk/extract-fa-fix
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2019-11-18
whitequark
Merge pull request #1494 from whitequark/write_verilog...
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2019-11-18
Marcin Kościelnicki
Fix #1496.
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2019-11-18
whitequark
write_verilog: add -extmem option, to write split memor...
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2019-11-17
Clifford Wolf
Merge pull request #1492 from YosysHQ/dave/wreduce...
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2019-11-16
Pepijn de Vos
Merge branch 'master' of https://github.com/YosysHQ...
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2019-11-15
David Shah
ecp5: Use new autoname pass for better cell/net names
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2019-11-14
David Shah
wreduce: Don't trim zeros or sext when not matching...
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2019-11-14
Clifford Wolf
Merge pull request #1490 from YosysHQ/clifford/autoname
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2019-11-14
Clifford Wolf
Merge pull request #1444 from btut/feature/python_wrapp...
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2019-11-14
Clifford Wolf
Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim
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2019-11-14
Clifford Wolf
Merge branch 'makaimann-label-bads-btor'
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2019-11-14
Clifford Wolf
Use cell name for btor bad state props when it is a...
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2019-11-14
Clifford Wolf
Merge branch 'label-bads-btor' of https://github.com...
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2019-11-13
Clifford Wolf
Add "autoname" pass and use it in "synth_ice40"
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2019-11-13
whitequark
Merge pull request #1488 from whitequark/flowmap-fixes
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2019-11-13
Clifford Wolf
Merge pull request #1486 from YosysHQ/clifford/fsmdetectfix
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2019-11-12
Clifford Wolf
Update fsm_detect bugfix
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2019-11-12
Clifford Wolf
Bugfix in fsm_detect
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2019-11-12
Clifford Wolf
Merge pull request #1484 from YosysHQ/clifford/cmp2luteqne
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2019-11-12
Makai Mann
Add an info string symbol for bad states in btor backend
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2019-11-12
whitequark
flowmap: when doing mincut, ensure source is always...
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2019-11-11
whitequark
flowmap: don't break if that creates a k+2 (and larger...
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2019-11-11
Pepijn de Vos
fix fsm test with proper clock enable polarity
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2019-11-11
Pepijn de Vos
Merge branch 'master' of https://github.com/YosysHQ...
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2019-11-11
Miodrag Milanovic
Fixed tests
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2019-11-11
Clifford Wolf
Do not map $eq and $ne in cmp2lut, only proper arithmet...
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2019-11-10
Clifford Wolf
Merge pull request #1470 from YosysHQ/clifford/subpassdoc
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2019-11-07
Clifford Wolf
Add check for valid macro names in macro definitions
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2019-11-06
Pepijn de Vos
fix wide luts
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2019-11-06
Marcin Kościelnicki
synth_xilinx: Merge blackbox primitive libraries.
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2019-11-04
Clifford Wolf
Fix write_aiger bug added in 524af21
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2019-10-31
Clifford Wolf
Add CodingReadme section on script passes
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2019-10-30
Pepijn de Vos
don't cound exact luts in big muxes; futile and fragile
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2019-10-28
Pepijn de Vos
add IOBUF
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2019-10-28
Pepijn de Vos
add tristate buffer and test
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2019-10-28
Pepijn de Vos
do not use wide luts in testcase
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2019-10-28
Pepijn de Vos
actually run the gowin tests
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2019-10-28
Pepijn de Vos
More formatting
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2019-10-28
Pepijn de Vos
really really fix formatting maybe
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2019-10-28
Pepijn de Vos
undo formatting fuckup
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2019-10-28
Pepijn de Vos
add wide luts
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2019-10-28
Pepijn de Vos
add 32-bit BRAM and byte-enables
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2019-10-27
Clifford Wolf
Merge pull request #1393 from whitequark/write_verilog...
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2019-10-24
Pepijn de Vos
ALU sim tweaks
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2019-10-24
Clifford Wolf
Improve naming scheme for (VHDL) modules imported from...
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2019-10-24
David Shah
Merge pull request #1455 from YosysHQ/dave/ultrascaleplus
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2019-10-24
Clifford Wolf
Add "verific -L"
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2019-10-23
David Shah
ice40: Add post-pnr ICESTORM_RAM model and fix FFs
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2019-10-23
David Shah
ice40: Support for post-pnr timing simulation
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2019-10-23
David Shah
xilinx: Add URAM288 mapping for xcup
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2019-10-23
David Shah
xilinx: Add support for UltraScale[+] BRAM mapping
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2019-10-22
Clifford Wolf
Bugfix in smtio vcd handling of $-identifiers
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2019-10-22
Marcin Kościelnicki
xilinx: Support multiplier mapping for all families.
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2019-10-22
Clifford Wolf
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
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2019-10-21
Pepijn de Vos
Add some tests
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2019-10-21
Pepijn de Vos
add a few more missing dff
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2019-10-21
Clifford Wolf
Add "verilog_defines -list" and "verilog_defines -reset"
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2019-10-21
Clifford Wolf
Fix handling of "restrict" in Verific front-end
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2019-10-21
Pepijn de Vos
add negedge DFF
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2019-10-21
Pepijn de Vos
use ADDSUB ALU mode to remove inverters
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2019-10-21
Pepijn de Vos
Merge branch 'master' of https://github.com/YosysHQ...
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2019-10-20
David Shah
ecp5: Pass -nomfs to abc9
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