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nmigen.git
2018-12-22 whitequarkhdl.xfrm: Abstract*Transformer→*Visitor commit | commitdiff | tree
2018-12-22 whitequarkback.rtlil: always initialize the entire memory. commit | commitdiff | tree
2018-12-22 whitequarkcompat: use nicer names for next_value/next_value_ce... commit | commitdiff | tree
2018-12-22 whitequarkhdl.mem: allow changing init value after creating memory. commit | commitdiff | tree
2018-12-22 whitequarkback.verilog: do not rename internal signals. commit | commitdiff | tree
2018-12-22 whitequarkcompat: fix confusing naming for memory port address... commit | commitdiff | tree
2018-12-22 whitequarkhdl.ir: fix port propagation between siblings, in the... commit | commitdiff | tree
2018-12-22 whitequarkcompat: do not finalize native submodules twice. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: use more informative signal naming for ports. commit | commitdiff | tree
2018-12-21 whitequarkhdl.ir: fix port propagation between siblings. commit | commitdiff | tree
2018-12-21 whitequarkcompat: provide verilog.convert shim. commit | commitdiff | tree
2018-12-21 whitequarkhdl.ir: do not flatten instances or collect ports from... commit | commitdiff | tree
2018-12-21 whitequarkcompat: provide Memory shim. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: ensure transparent read port model has correct... commit | commitdiff | tree
2018-12-21 whitequarkback.pysim: handle out of bounds ArrayProxy indexes. commit | commitdiff | tree
2018-12-21 whitequarkback.pysim: give numeric names to unnamed subfragments... commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: use different naming for array signals. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: add simulation model for memory. commit | commitdiff | tree
2018-12-21 whitequarkback.pysim: fix an issue with too few funclet slots. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: add tests for all error conditions. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: tie rdport.en high for asynchronous or transpa... commit | commitdiff | tree
2018-12-21 whitequarkback.rtlil: more consistent prefixing for subfragment... commit | commitdiff | tree
2018-12-21 whitequarkhdl.ir: correctly handle named output and inout ports. commit | commitdiff | tree
2018-12-21 whitequarkback.rtlil: implement memories. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: implement memories. commit | commitdiff | tree
2018-12-21 whitequarkback.rtlil: explicitly pad constants with zeroes. commit | commitdiff | tree
2018-12-21 whitequarkback.rtlil: fix translation of Cat. commit | commitdiff | tree
2018-12-20 whitequarkir: allow non-Signals in Instance ports. commit | commitdiff | tree
2018-12-19 whitequarksetup: update pyvcd dependency, for var_type="string". commit | commitdiff | tree
2018-12-18 whitequarkcompat: import genlib.record from Migen. commit | commitdiff | tree
2018-12-18 whitequarkcompat: add wrappers for Slice.stop, Cat.l, _ArrayProxy... commit | commitdiff | tree
2018-12-18 whitequarkhdl.ast: Cat.{operands→parts} commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: implement *. commit | commitdiff | tree
2018-12-18 whitequarktest.sim: add tests for sync functionality and errors. commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: eliminate most dictionary lookups. commit | commitdiff | tree
2018-12-18 whitequarkhdl.ast, hdl.xfrm: various microoptimizations to speed... commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: use arrays instead of dicts for signal... commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: naming. NFC. commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: fix an off-by-1 in add_sync_process(). commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: trigger processes waiting on Tick() exactly... commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: continue running simulator processes until... commit | commitdiff | tree
2018-12-18 whitequarkTravis: cache Yosys installation explicitly. commit | commitdiff | tree
2018-12-17 whitequarkfhdl.ir: add black-box fragments, fragment parameters... commit | commitdiff | tree
2018-12-17 whitequarkTravis: build and cache Yosys. commit | commitdiff | tree
2018-12-17 whitequarkhdl, back: add and use SignalSet/SignalDict. commit | commitdiff | tree
2018-12-17 whitequarkhdl.ast: factor out _MappedKeyDict, _MappedKeySet.... commit | commitdiff | tree
2018-12-17 whitequarkback.rtlil: update for Yosys master. commit | commitdiff | tree
2018-12-17 whitequarkback.rtlil: implement Array. commit | commitdiff | tree
2018-12-17 whitequarkback.rtlil: implement Part. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: handle reset_less domains. commit | commitdiff | tree
2018-12-16 whitequarkhdl.dsl: add clock domain support. commit | commitdiff | tree
2018-12-16 whitequarkhdl.dsl: cleanup. NFC. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: extract _StatementCompiler. NFC. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: simplify. NFC. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: properly escape strings in attributes. commit | commitdiff | tree
2018-12-16 whitequarkREADME: mention Yosys requirement. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: prepare for Yosys sigspec slicing improvements. commit | commitdiff | tree
2018-12-16 whitequarkcompat.fhdl.structure: only convert to bool in If/Elif... commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: avoid illegal slices. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: use slicing to match shape when reducing... commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: don't emit a slice if all bits are used. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: reorganize value compiler into LHS/RHS. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: fix naming. NFC. commit | commitdiff | tree
2018-12-16 whitequarkhdl.xfrm: separate AST traversal from AST identity... commit | commitdiff | tree
2018-12-16 whitequarkcompat.fhdl: reexport Array. commit | commitdiff | tree
2018-12-16 whitequarkback.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. commit | commitdiff | tree
2018-12-15 whitequarktest.sim: generalize assertOperator. NFC. commit | commitdiff | tree
2018-12-15 whitequarkback.pysim: add (stub) LHSValueCompiler. commit | commitdiff | tree
2018-12-15 whitequarkback.pysim: implement Part. commit | commitdiff | tree
2018-12-15 whitequarkexamples: rename clkdiv/ctrl to ctr/ctr_ce. commit | commitdiff | tree
2018-12-15 whitequarkdoc: update COMPAT_SUMMARY. commit | commitdiff | tree
2018-12-15 whitequarkback.pysim: implement ArrayProxy. commit | commitdiff | tree
2018-12-15 whitequarkhdl.ast: implement Array and ArrayProxy. commit | commitdiff | tree
2018-12-15 whitequarkLower Python version requirement to 3.6. commit | commitdiff | tree
2018-12-15 whitequarkhdl: appropriately rename tests. NFC. commit | commitdiff | tree
2018-12-15 whitequarkhdl.ast: improve ClockSignal, ResetSignal documentation. commit | commitdiff | tree
2018-12-15 whitequarkRename fhdl→hdl, genlib→lib. commit | commitdiff | tree
2018-12-15 whitequarkMove star imports to make `from nmigen import *` usable. commit | commitdiff | tree
2018-12-15 whitequarkdoc: fix some Markdown awkwardness. commit | commitdiff | tree
2018-12-15 whitequarkdoc: update COMPAT_SUMMARY to reflect actual status. commit | commitdiff | tree
2018-12-15 whitequarkDetermine Migen's API surface and document compatibilit... commit | commitdiff | tree
2018-12-15 whitequarkpyback.sim: test Slice, Cat, Repl. commit | commitdiff | tree
2018-12-15 whitequarkfhdl.ast, back.pysim: implement shifts. commit | commitdiff | tree
2018-12-15 whitequarkfhdl.ast: refactor Operator.shape(). NFC. commit | commitdiff | tree
2018-12-15 whitequarkConsistently use '{!r}' in and only in TypeError messages. commit | commitdiff | tree
2018-12-15 whitequarkfhdl.ir: test iter_comb(), iter_sync() and iter_signals(). commit | commitdiff | tree
2018-12-15 whitequarkfhdl.ir: fix incorrect uses of positive to say non... commit | commitdiff | tree
2018-12-15 whitequarkcompat.fhdl.structure: handle If/Elif with multi-bit... commit | commitdiff | tree
2018-12-14 whitequarkcompat.fhdl.module: allow adding native submodules... commit | commitdiff | tree
2018-12-14 whitequarkFix deprecations in Python 3.7. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: preserve process locations through add_sync... commit | commitdiff | tree
2018-12-14 whitequarkfhdl.ast: clean up stub error messages. NFC. commit | commitdiff | tree
2018-12-14 whitequarkfhdl.ir: automatically flatten hierarchy to resolve... commit | commitdiff | tree
2018-12-14 whitequarkfhdl.ir: Fragment.{drive→add_driver} commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: count delta cycles separately to avoid... commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: simplify. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: revert 70ebc6f2. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: fix implicit boolean conversion. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: squash one level of hierarchy. commit | commitdiff | tree
2018-12-14 whitequarkback.pysim: implement blocking assignment semantics... commit | commitdiff | tree
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