yosys.git
2021-01-27 Yosys BotBump version
2021-01-26 Marcelina Kościelnickaxilinx_dffopt: Don't crash on missing IS_*_INVERTED.
2021-01-26 Marcelina Kościelnickaxilinx: Add FDRSE_1, FDCPE_1.
2021-01-26 whitequarkMerge pull request #2563 from whitequark/cxxrtl-msvc
2021-01-26 whitequarkMerge pull request #2544 from modwizcode/fix-clock
2021-01-26 whitequarkcxxrtl: do not use `->template` for non-dependent names.
2021-01-26 Yosys BotBump version
2021-01-25 whitequarkMerge pull request #2549 from pgadfort/support-multiple...
2021-01-25 whitequarkMerge pull request #2550 from zachjs/macro-arg-spaces
2021-01-25 Yosys BotBump version
2021-01-24 Claire XenMerge pull request #2558 from YosysHQ/dave/chandle-dpi
2021-01-23 David Shahdpi: Support for chandle type
2021-01-22 Yosys BotBump version
2021-01-21 Miodrag MilanovićMerge pull request #2553 from zachjs/rand-const-modifiers
2021-01-21 Zachary SnowAllow combination of rand and const modifiers
2021-01-21 Yosys BotBump version
2021-01-20 Claire XenMerge pull request #2552 from YosysHQ/claire/yosyshq
2021-01-20 Claire Xenia... Switch verific bindings from Symbiotic EDA flavored...
2021-01-20 Miodrag MilanovićMerge pull request #2536 from TobiasFaller/master
2021-01-20 Miodrag MilanovićMerge pull request #2551 from zachjs/wire-logic
2021-01-20 Zachary Snowsv: fix support wire and var data type modifiers
2021-01-20 Zachary Snowverilog: allow spaces in macro arguments
2021-01-19 Yosys BotBump version
2021-01-18 Peter Gadfortadding support for passing multiple liberty files to abc
2021-01-18 whitequarkMerge pull request #2547 from zachjs/plugin-so-dsym
2021-01-18 whitequarkMerge pull request #2312 from antmicro/typedef-inout
2021-01-18 Zachary SnowAdd plugin.so.dSYM to .gitignore
2021-01-18 Kamil RakoczyAdd typedef input/output test
2021-01-18 Kamil RakoczyFix input/output attributes when resolving typedef...
2021-01-18 Lukasz DalekParse package user type in module port list
2021-01-15 Iris JohnsonImproves the previous commit with a more complete cover...
2021-01-15 Yosys BotBump version
2021-01-14 Iris JohnsonHandle sliced bits as clock inputs (fixes #2542)
2021-01-14 Marcelina Kościelnickaopt_share: Fix X and CO signal width for shifted $alu...
2021-01-14 Yosys BotBump version
2021-01-13 Claire XenMerge pull request #2537 from pepijndevos/spice
2021-01-13 Pepijn de Vosadd buffer option to spice backend
2021-01-12 Tobias FallerFixed missing goto statement in passes/techmap/abc.cc
2021-01-05 Yosys BotBump version
2021-01-04 whitequarkMerge pull request #2522 from tomverbeure/simlib_typos2
2021-01-04 Tom VerbeureFix some trivial typos.
2021-01-02 Yosys BotBump version
2021-01-01 whitequarkMerge pull request #2480 from YosysHQ/dave/nexus-lram
2021-01-01 whitequarkMerge pull request #2512 from umarcor/plugin-err
2021-01-01 whitequarkMerge pull request #2515 from umarcor/fix/ghdl
2021-01-01 whitequarkMerge pull request #2518 from zachjs/recursion
2021-01-01 whitequarkMerge pull request #2517 from zachjs/sv-tf-implied...
2021-01-01 Zachary Snowverilog: improved support for recursive functions
2020-12-31 Zachary Snowsv: complete support for implied task/function port...
2020-12-30 umarcormakefile: fix GHDL vars, replace GHDL_DIR with GHDL_PREFIX
2020-12-30 Yosys BotBump version
2020-12-29 umarcorplugin: enhance no-plugin error
2020-12-29 whitequarkMerge pull request #2509 from zachjs/issue-2427
2020-12-29 whitequarkMerge pull request #2514 from umarcor/feat/ghdl
2020-12-29 Yosys BotBump version
2020-12-28 umarcormakefile: add support for built-in ghdl-yosys-plugin
2020-12-28 whitequarkMerge pull request #2511 from umarcor/feat/msys2-32
2020-12-28 whitequarkMerge pull request #2507 from umarcor/fix/msys2
2020-12-28 umarcormakefile: rename msys2 to msys2-32, config PREFIX
2020-12-28 umarcorkernel/yosys.h: undef CONST on WIN32
2020-12-28 Yosys BotBump version
2020-12-27 Claire XenMerge pull request #2510 from YosysHQ/whitequark/CODEOW...
2020-12-27 whitequarkCODEOWNERS: add @zachjs as Verilog/AST frontend owner
2020-12-27 Zachary SnowFix elaboration of whole memory words used as indices
2020-12-27 Yosys BotBump version
2020-12-26 Miodrag MilanovićMerge pull request #2506 from zachjs/const-arg-redeclare
2020-12-26 Zachary SnowFix constants bound to redeclared function args
2020-12-24 Yosys BotBump version
2020-12-23 whitequarkMerge pull request #2502 from ldoolitt/master
2020-12-23 whitequarkMerge pull request #2501 from zachjs/genrtlil-tern...
2020-12-23 whitequarkMerge pull request #2476 from zachjs/const-arg-width
2020-12-23 Larry Doolittlepasses/pmgen/pmgen.py: trivial change to remove C+...
2020-12-23 Zachary Snowgenrtlil: fix mux2rtlil generated wire signedness
2020-12-23 Yosys BotBump version
2020-12-23 Zachary SnowFix constants bound to single bit arguments (fixes...
2020-12-22 whitequarkMerge pull request #2499 from whitequark/cxxrtl-fixes
2020-12-22 whitequarkcxxrtl: don't crash generating debug information for...
2020-12-22 whitequarkMerge pull request #2498 from StefanBruens/Fix_opt_lut
2020-12-22 whitequarkMerge pull request #2497 from whitequark/cxxrtl-reflow
2020-12-22 whitequarkcxxrtl: split processes into sync and case nodes.
2020-12-22 whitequarkkernel: undef Tcl macros interfering with cxxrtl.
2020-12-22 whitequarkcxxrtl: completely rewrite netlist layout code.
2020-12-22 StefanBruensFix use-after-free in LUT opt pass
2020-12-22 whitequarkMerge pull request #2479 from zachjs/const-arg-hint
2020-12-22 whitequarkMerge pull request #2491 from zachjs/port-bind-sign
2020-12-22 Yosys BotBump version
2020-12-21 whitequarkcxxrtl: simplify logic choosing wire type. NFCI.
2020-12-21 whitequarkcxxrtl: clarify node use-def construction. NFCI.
2020-12-21 whitequarkcxxrtl: fix typo.
2020-12-21 Marcelina Kościelnickaxilinx: Add some missing blackbox cells.
2020-12-21 Marcelina Kościelnickaxilinx: Regenerate cells_xtra.v using Vivado 2020.2
2020-12-21 whitequarkMerge pull request #2496 from whitequark/cxxrtl-fixes
2020-12-21 whitequarkcxxrtl: speed up bit repeats (sign extends, etc).
2020-12-21 whitequarkcxxrtl: speed up commits on clang.
2020-12-20 whitequarkcxxrtl: use `static inline` instead of `inline` in...
2020-12-20 Yosys BotBump version
2020-12-19 whitequarkMerge pull request #2487 from whitequark/cxxrtl-outlining
2020-12-19 Zachary SnowSign extend port connections where necessary
2020-12-18 Yosys BotBump version
2020-12-17 Marcelina Kościelnickaxilinx: Add FDDRCPE and FDDRRSE blackbox cells.
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