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yosys.git
2022-05-12
Marcelina Kościelnicka
Add proc_rom pass.
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2022-05-10
github-actions...
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2022-05-09
Jannis Harder
Merge pull request #3305 from jix/sva_value_change_logic
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2022-05-09
Jannis Harder
Merge pull request #3297 from jix/sva_nested_clk_else
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2022-05-09
Jannis Harder
verific: Improve logic generated for SVA value change...
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2022-05-09
Miodrag Milanovic
Next dev cycle
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2022-05-09
Miodrag Milanovic
Release version 0.17
yosys-0.17
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2022-05-09
Miodrag Milanovic
Update CHANGELOG
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2022-05-09
Miodrag Milanovic
Update manual
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2022-05-09
Miodrag Milanović
Merge pull request #3299 from YosysHQ/mmicko/sim_memory
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2022-05-09
Miodrag Milanovic
Fix running sva tests
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2022-05-08
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2022-05-07
Marcelina Kościelnicka
opt_mem: Remove constant-value bit lanes.
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2022-05-07
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2022-05-06
Miodrag Milanovic
include latest abc changes
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2022-05-06
Miodrag Milanovic
include latest abc changes
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2022-05-06
Miodrag Milanović
Merge pull request #3300 from imhcyx/master
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2022-05-06
Miodrag Milanovic
Include abc change to fix FreeBSD build
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2022-05-06
Miodrag Milanovic
Handle possible non-memory indexed data
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2022-05-05
imhcyx
memory_share: fix wrong argidx in extra_args
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2022-05-05
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2022-05-04
Marcelina Kościelnicka
abc: Use dict/pool instead of std::map/std::set
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2022-05-04
Miodrag Milanovic
map memory location to wire value, if memory is convert...
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2022-05-04
Miodrag Milanovic
fix crash when no fst input
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2022-05-04
Miodrag Milanovic
Start restoring memory state from VCD/FST
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2022-05-04
Claire Xenia...
Add propagated clock signals into btor info file
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2022-05-03
Jannis Harder
verific: Fix conditions of SVAs with explicit clocks...
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2022-05-03
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2022-05-02
Miodrag Milanovic
AIM file could have gaps in or between inputs and inits
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2022-04-30
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2022-04-29
Miodrag Milanović
Merge pull request #3294 from YosysHQ/micko/verific_mer...
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2022-04-29
Miodrag Milanovic
Ignore merging past ffs that we are not properly merging
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2022-04-26
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2022-04-25
Rick Luiken
Add missing parameters for ecp5
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2022-04-25
Jannis Harder
Merge pull request #3287 from jix/smt2-conditional...
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2022-04-25
Jannis Harder
Merge pull request #3257 from jix/tribuf-formal
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2022-04-25
Miodrag Milanović
Merge pull request #3290 from mpasternacki/bugfix/freeb...
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2022-04-25
Miodrag Milanović
Merge pull request #3289 from YosysHQ/micko/sim_improve
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2022-04-24
Maciej Pasternacki
Fix build on FreeBSD, which has no alloca.h
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2022-04-22
Miodrag Milanovic
Match $anyseq input if connected to public wire
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2022-04-22
Miodrag Milanovic
Treat $anyseq as input from FST
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2022-04-22
Miodrag Milanovic
Ignore change on last edge
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2022-04-22
Miodrag Milanovic
Last sample from input does not represent change
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2022-04-22
Miodrag Milanovic
latches are always set to zero
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2022-04-22
Miodrag Milanovic
If not multiclock, output only on clock edges
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2022-04-22
Miodrag Milanovic
Set init state for all wires from FST and set past
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2022-04-22
Miodrag Milanovic
Fix multiclock for btor2 witness
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2022-04-20
Jannis Harder
smt2: Make write port array stores conditional on nonze...
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2022-04-19
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2022-04-18
Miodrag Milanović
Merge pull request #3280 from YosysHQ/micko/fix_readaiw
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2022-04-18
Miodrag Milanovic
Update abc
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2022-04-18
Miodrag Milanovic
verific: allow memories to be inferred in loops (vhdl)
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2022-04-18
Miodrag Milanović
Merge pull request #3282 from nakengelhardt/verific_loo...
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2022-04-16
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2022-04-15
Marcelina Kościelnicka
memory_share: Fix up mismatched address widths.
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2022-04-15
Marcelina Kościelnicka
opt_dff: Fix behavior on $ff with D == Q.
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2022-04-15
N. Engelhardt
verific: allow memories to be inferred in loops
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2022-04-15
Miodrag Milanovic
Fix reading aiw from other solvers
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2022-04-12
Jannis Harder
tribuf: `-formal` option: convert all to logic and...
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2022-04-09
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2022-04-08
Miodrag Milanović
Merge pull request #3275 from YosysHQ/micko/clk2fflogic_fix
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2022-04-08
Miodrag Milanovic
Use wrap_async_control_gate if ff is fine
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2022-04-08
Miodrag Milanović
Merge pull request #3273 from modwizcode/fix-build
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2022-04-08
Aki Van Ness
pass jny: flipped the defaults for the inclusion of...
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2022-04-08
Aki Van Ness
pass jny: ensured the cell collection is cleared betwee...
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2022-04-08
Aki Van Ness
pass jny: fixed missing quotes around the type value...
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2022-04-08
Aki Van Ness
pass jny: fixed the backslash escape for strings
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2022-04-08
Aki Van Ness
pass jny: removed the invalid json escapes
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2022-04-08
Aki Van Ness
pass jny: added some todo comments about things that...
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2022-04-08
Aki Van Ness
pass jny: changed the constructor initializers to use...
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2022-04-08
Aki Van Ness
pass jny: fixed the string escape method to be less...
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2022-04-08
Aki Van Ness
pass jny: fixed the signed output for param value output
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2022-04-08
Aki Van Ness
pass jny: added connection output
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2022-04-08
Aki Van Ness
pass jny: added filter options for including connection...
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2022-04-08
Aki Van Ness
pass jny: large chunk of refactoring to make the JSON...
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2022-04-08
Aki Van Ness
metadata -> jny: migrated to the proper name for the...
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2022-04-08
Aki Van Ness
pass metadata: added the machinery to write param and...
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2022-04-08
Aki Van Ness
pass metadata: removed superfluous `stringf` calls
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2022-04-08
Aki Van Ness
pass metadata: some more rough work on dumping the...
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2022-04-08
Aki Van Ness
pass metadata: fixed the MetadataWriter object initiali...
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2022-04-08
Aki Van Ness
pass metadata: added the output of parameters,
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2022-04-08
Aki Van Ness
pass metadata: fixed some of the output formatting
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2022-04-08
Aki Van Ness
pass metadata: initial commit of the metadata pass...
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2022-04-08
Iris Johnson
Makefile: properly conditionalize features requiring...
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2022-04-08
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2022-04-07
Catherine
Merge pull request #3269 from YosysHQ/micko/fix_autotop
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2022-04-07
Marcelina Kościelnicka
abc: Add support for FFs with reset in -dff
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2022-04-06
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2022-04-05
Zachary Snow
sv: fix always_comb auto nosync for nested and function...
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2022-04-05
Miodrag Milanovic
Reorder steps in -auto-top to fix synth command, fixes...
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2022-04-05
Miodrag Milanovic
Next dev cycle
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2022-04-05
Miodrag Milanovic
Release version 0.16
yosys-0.16
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2022-04-05
github-actions...
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2022-04-04
Marcelina Kościelnicka
show: Fix width labels.
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2022-04-04
Miodrag Milanovic
Update CHANGELOG and manual
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2022-04-04
Miodrag Milanović
Merge pull request #3265 from YosysHQ/micko/sim_improve...
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2022-04-02
Miodrag Milanovic
past_ad initial value setting
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2022-04-02
Miodrag Milanovic
setInitState can be only one altering values
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2022-04-02
Miodrag Milanovic
Set past_d value for init state
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2022-04-02
Jannis Harder
Merge pull request #3264 from jix/invalid_ff_dcinit_merge
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