yosys.git
2014-09-01 Clifford WolfFixed "test_cell -simlib all"
2014-09-01 Clifford WolfAdded "test_cell -simlib -v"
2014-09-01 Clifford WolfAdded "techmap -autoproc"
2014-09-01 Clifford WolfFixes in old SAT example.ys
2014-09-01 Clifford WolfMoved "share" and "wreduce" to passes/opt/
2014-09-01 Clifford WolfUsing std::vector<RTLIL::State> instead of RTLIL::Const...
2014-08-31 Clifford WolfAdded eval testing to test_cell
2014-08-31 Clifford WolfFixed return size of const_*() eval functions
2014-08-31 Clifford WolfAdded RTLIL::Const::size()
2014-08-31 Clifford WolfAdded eval model for $lut cells
2014-08-31 Clifford WolfTypo fixes in cell->*Param() API
2014-08-31 Clifford WolfAdded $lut support in test_cell, techmap, satgen
2014-08-30 Clifford WolfAdded design->scratchpad
2014-08-30 Clifford WolfAdded $alu cell type
2014-08-30 Clifford WolfAdded autotest -e (do not use -noexpr on write_verilog)
2014-08-30 Clifford WolfImproved write address decoder generation memory_map
2014-08-30 Clifford WolfFixed module->addPmux()
2014-08-30 Clifford WolfUsing worker class in memory_map
2014-08-30 Clifford WolfReplaced $__alu CO/CS outputs with full-width CO output
2014-08-30 Clifford WolfDon't change existing binary FSM encoding if it is...
2014-08-30 Clifford WolfUsing $pmux info in fsm_extract to optimize transition...
2014-08-30 Clifford WolfImproved handling of $pmux cells in fsm_extract
2014-08-27 Clifford WolfFixed inserting of Q-inverters in dfflibmap
2014-08-27 Clifford WolfFixed printing of multi-line Makefile.conf
2014-08-26 Clifford WolfImplemented "rename -enumerate -pattern"
2014-08-26 Clifford WolfPrint Makefile.conf as make info message
2014-08-25 Clifford WolfChecking for valid CONFIG value in Makefile
2014-08-24 Clifford WolfOptimize shift ops with constant rhs in opt_const
2014-08-24 Clifford WolfAdded some additional log messages to opt_const
2014-08-24 Clifford WolfAdded is_signed argument to SigSpec.as_int() and Const...
2014-08-24 Clifford Wolfazonenberg: Make dump_vcd save model when temporal...
2014-08-23 Clifford WolfOnly call proc_share_dirname() in techmap when necessary
2014-08-23 Clifford WolfRemoved compatbility.{h,cc}: Not using open_memstream...
2014-08-23 Clifford WolfChanged frontend-api from FILE to std::istream
2014-08-23 Clifford WolfChanged backend-api from FILE to std::ostream
2014-08-22 Clifford WolfAdded "stat -width"
2014-08-22 Clifford WolfAdded emscripten (emcc) support to build system and...
2014-08-22 Clifford WolfAdded DPI-C documentation to README file
2014-08-22 Clifford WolfAdded support for non-standard <plugin>:<c_name> DPI...
2014-08-22 Clifford WolfArchibald Rust and Clifford Wolf: ffi-based dpi_call()
2014-08-22 Clifford WolfAdded "plugin" command
2014-08-22 Clifford WolfUpdated ABC to 4d547a5e065b
2014-08-21 Clifford WolfCosmetic changes to FSM tests
2014-08-21 Clifford WolfFixed small memory leak in ast simplify
2014-08-21 Clifford WolfAdded support for DPI function with different names...
2014-08-21 Clifford WolfAdded AstNode::asInt()
2014-08-21 Clifford WolfFixed memory leak in DPI function calls
2014-08-21 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-08-21 Clifford WolfAdded Verilog/AST support for DPI functions (dpi_call...
2014-08-21 Clifford WolfAdded support for global tasks and functions
2014-08-19 Clifford WolfAdded mod->addGate() methods for new gate types
2014-08-18 Clifford WolfUsing "via_celltype" in $mul carry-save-acc implementation
2014-08-18 Clifford WolfAdded "via_celltype" attribute on task/func
2014-08-17 Clifford WolfPerformance fix for new $__lcu techmap rule
2014-08-17 Clifford WolfReplaced recursive lcu scheme with bk adder
2014-08-17 Clifford WolfAdded const folding of AST_CASE to AST simplifier
2014-08-17 Clifford WolfFixed proc_{self,share}_dirname error handling
2014-08-17 Clifford WolfMakefile fixes
2014-08-17 Clifford WolfImproved AST ProcessGenerator performance
2014-08-17 Clifford WolfImproved sig.remove2() performance
2014-08-16 Clifford WolfUse stackmap<> in AST ProcessGenerator
2014-08-16 Clifford WolfAdded stackmap<> container
2014-08-16 Clifford WolfRenamed toposort.h to utils.h
2014-08-16 Clifford WolfAdded module->uniquify()
2014-08-16 Clifford WolfFixed AOI/OAI expr handling in verilog backend
2014-08-16 Clifford WolfMultiply using a carry-save accumulator
2014-08-16 Clifford WolfAdded "test_cell -s <seed>"
2014-08-16 Clifford WolfAST ProcessGenerator: replaced subst_*_{from,to} with...
2014-08-16 Clifford WolfAdded additional gate types: $_NAND_ $_NOR_ $_XNOR_...
2014-08-16 Clifford WolfAdded CellTypes::cell_evaluable()
2014-08-16 Clifford WolfChanges in techmap $__alu interface
2014-08-16 Clifford WolfAdded "opt -fast"
2014-08-16 Clifford WolfAdded log_spacer()
2014-08-15 Clifford WolfBugfix in iopadmap
2014-08-15 Clifford WolfRenamed $lut ports to follow A-Y naming scheme
2014-08-15 Clifford WolfRenamed $_INV_ cell type to $_NOT_
2014-08-15 Clifford WolfRemoved old doc references to $safe_pmux
2014-08-15 Clifford WolfMore idstring sort_by_* helpers and fixed tpl ordering...
2014-08-15 Clifford WolfAdded Frontend "+/" filename syntax for files from...
2014-08-15 Clifford Wolfdocument "techmap -map %<design-name>"
2014-08-14 Clifford WolfFixed bug in "read_verilog -ignore_redef"
2014-08-14 Clifford WolfAdded RTLIL::SigSpec::to_sigbit_map()
2014-08-14 Clifford WolfChanged the AST genWidthRTLIL subst interface to use...
2014-08-14 Clifford WolfAdded sig.{replace,remove,extract} variants for std...
2014-08-14 Clifford WolfFixed line numbers when using here-doc macros
2014-08-14 Clifford WolfFixed handling of task outputs
2014-08-14 Clifford WolfSimplified $__arraymul techmap rule
2014-08-14 Clifford WolfAdded module->ports
2014-08-14 Clifford WolfRefactoring of CellType class
2014-08-14 Clifford WolfRIP $safe_pmux
2014-08-14 Clifford WolfSome improvements in FSM mapping and recoding
2014-08-14 Clifford WolfAdded "abc -D" for setting delay target
2014-08-14 Clifford WolfUpdated ABC to 4935c2b946de
2014-08-13 Clifford WolfAdded techmap support for actual lookahead carry unit
2014-08-13 Clifford WolfPreparations for lookahead ALU support in techmap.v
2014-08-13 Clifford WolfFilter ANSI escape sequences from ABC output
2014-08-13 Clifford WolfNew interface for $__alu in techmap.v
2014-08-13 Clifford WolfAdded support for non-standard """ macro bodies
2014-08-12 Clifford WolfFixed handling of constant-true branches in proc_clean
2014-08-12 Clifford WolfAdded test_verific mode to tests/fsm/generate.py
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