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yosys.git
2017-08-27
Robert Ou
recover_reduce: Add driver script for the $reduce_...
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2017-08-27
Robert Ou
recover_reduce_core: Finish implementing the core function
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2017-08-27
Robert Ou
recover_reduce_core: Initial commit
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2017-08-25
Clifford Wolf
Don't track , ... contradictions through x/z-bits
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2017-08-25
Clifford Wolf
Add removing of redundant pairs of bits in ==, ===...
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2017-08-25
Clifford Wolf
Merge branch 'extract_fa'
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2017-08-25
Clifford Wolf
Further improve extract_fa (seems to be fully functiona...
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2017-08-25
Clifford Wolf
Rename "adders" to "extract_fa"
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2017-08-25
Clifford Wolf
Fix bug in write_smt2 (export logic driving hierarchica...
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2017-08-23
Clifford Wolf
Towards more generic "adder" function extractor
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2017-08-22
Clifford Wolf
Add experimental adders pass
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2017-08-22
Clifford Wolf
Add hashlib support for hashing of pools
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2017-08-22
Clifford Wolf
Add consteval support for $_ANDNOT_ and $_ORNOT_
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2017-08-21
Clifford Wolf
Remove some dead code from fsm_map
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2017-08-20
Clifford Wolf
Rename "singleton" pass to "uniquify"
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2017-08-18
Clifford Wolf
More intuitive handling of "cd .." for singleton modules
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2017-08-18
Clifford Wolf
Add "sim -zinit -rstlen"
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2017-08-18
Clifford Wolf
Merge branch 'sim'
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2017-08-18
Clifford Wolf
Add "sim" support for memories
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2017-08-18
Clifford Wolf
Add Const methods is_fully_zero(), is_fully_def(),...
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2017-08-18
Clifford Wolf
Add support for assert/assume/cover to "sim" command
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2017-08-17
Clifford Wolf
Add writeback mode to "sim" command
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2017-08-17
Clifford Wolf
Improve "sim" command
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2017-08-16
Clifford Wolf
Merge pull request #386 from azonenberg/gpak-counters
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2017-08-16
Clifford Wolf
Add "sim" command skeleton
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2017-08-15
Andrew Zonenberg
Fixed more issues with GreenPAK counter sim models
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2017-08-15
Andrew Zonenberg
Updated PGEN model to have level triggered reset (match...
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2017-08-15
Andrew Zonenberg
Fixed bug in GP_COUNTx model
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2017-08-15
Andrew Zonenberg
Fixed bug where GP_COUNTx_ADV would wrap even when...
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2017-08-15
Clifford Wolf
Merge branch 'azonenberg-rmports'
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2017-08-15
Clifford Wolf
Mostly coding style related fixes in rmports pass
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2017-08-15
Clifford Wolf
Merge branch 'rmports' of https://github.com/azonenberg...
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2017-08-14
Clifford Wolf
Merge pull request #381 from azonenberg/countfix
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2017-08-14
Clifford Wolf
Merge pull request #383 from azonenberg/abcfnames
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2017-08-14
Clifford Wolf
Merge pull request #382 from azonenberg/jsoniofix
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2017-08-14
Clifford Wolf
Merge pull request #384 from azonenberg/crtechlib
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2017-08-14
Robert Ou
coolrunner2: Add INVERT parameter to some BUFGs
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2017-08-14
Robert Ou
coolrunner2: Add FFs with clock enable to cells_sim.v
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2017-08-14
Robert Ou
abc: Allow +/ filenames in the abc command
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2017-08-14
Robert Ou
json: Parse inout correctly rather than as an output
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2017-08-14
Andrew Zonenberg
rmports: Now remove ports from cell instances if we...
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2017-08-14
Andrew Zonenberg
ProcessModule is no longer virtual (why was it in the...
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2017-08-14
Andrew Zonenberg
rmports now works on all modules in the design, not...
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2017-08-14
Andrew Zonenberg
Updated Makefile to reflect opt_rmports being renamed...
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2017-08-14
Andrew Zonenberg
Renamed opt_rmports pass to rmports
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2017-08-14
Andrew Zonenberg
Fixed typo in GP_COUNT8 sim model
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2017-08-14
Andrew Zonenberg
Fixed typo in error message
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2017-08-14
Andrew Zonenberg
Changed LEVEL resets for GP_COUNTx to be properly synth...
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2017-08-14
Andrew Zonenberg
Changed LEVEL resets to be edge triggered anyway
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2017-08-14
Andrew Zonenberg
Added level-triggered reset support to GP_COUNTx simula...
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2017-08-14
Andrew Zonenberg
Fixed undeclared "count" in GP_COUNT8_ADV
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2017-08-14
Andrew Zonenberg
Fixed undeclared "count" in GP_COUNT14_ADV
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2017-08-14
Andrew Zonenberg
Fixed typo in last commit
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2017-08-14
Andrew Zonenberg
Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models...
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2017-08-14
Andrew Zonenberg
Fixed typo in COUNT8 model
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2017-08-14
Andrew Zonenberg
Moved GP_POR out of digital cells b/c it has delays
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2017-08-14
Andrew Zonenberg
Improved cells_sim_digital model for GP_COUNT8
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2017-08-14
Andrew Zonenberg
Refactored GreenPAK4 cells_sim into cells_sim_ams and...
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2017-08-14
Andrew Zonenberg
Improved handling of constant connections in opt_rmports
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2017-08-14
Andrew Zonenberg
Fixed handling of cell ports that aren't wires
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2017-08-14
Andrew Zonenberg
opt_rmports: Fixed incorrect handling of multi-bit...
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2017-08-14
Andrew Zonenberg
Removed commented out debug code
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2017-08-14
Andrew Zonenberg
Added opt_rmports pass (remove unconnected ports from...
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2017-08-09
Clifford Wolf
Add support for set-reset cell variants to opt_rmdff
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2017-08-09
Clifford Wolf
Auto-detect JSON front-end
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2017-08-06
Clifford Wolf
Add handling of constant reset signals to opt_rmdff
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2017-08-04
Clifford Wolf
Add "yosys-smtbmc --smtc-init --smtc-top --noinit"
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2017-08-04
Clifford Wolf
Add "-undefined dynamic_lookup" to OSX "yosys-config...
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2017-07-29
Clifford Wolf
Fix typo in "abc" pass help message
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2017-07-28
Clifford Wolf
Add merging of "past FFs" to verific importer
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2017-07-28
Clifford Wolf
Add consolidation of init attributes to opt_clean,...
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2017-07-28
Clifford Wolf
Add minimal support for PSL in VHDL via Verific
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2017-07-28
Clifford Wolf
Add simple VHDL+PSL example
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2017-07-28
Clifford Wolf
Improve Verific HDL language options
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2017-07-28
Clifford Wolf
Fix handling of non-user-declared Verific netbus
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2017-07-27
Clifford Wolf
Improve Verific SVA importer
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2017-07-27
Clifford Wolf
Add counter.sv SVA test
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2017-07-27
Clifford Wolf
Add log_warning_noprefix() API, Use for Verific warning...
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2017-07-27
Clifford Wolf
Add "verific -import -n" and "verific -import -nosva"
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2017-07-27
Clifford Wolf
Improve SVA tests, add Makefile and scripts
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2017-07-27
Clifford Wolf
Improve Verific SVA import: negedge and $past
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2017-07-27
Clifford Wolf
Improve Verific SVA importer
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2017-07-26
Clifford Wolf
Add "opt_expr -fine" feature to remove neutral bits...
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2017-07-26
Clifford Wolf
Improve Verific bindings (mostly related to SVA)
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2017-07-25
Clifford Wolf
Improve "help verific" message
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2017-07-25
Clifford Wolf
Add "verific -extnets"
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2017-07-25
Clifford Wolf
Add "using std::get" to yosys.h
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2017-07-25
Clifford Wolf
Improve "verific -all" handling
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2017-07-24
Clifford Wolf
Add "verific -import -d <dump_file"
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2017-07-24
Clifford Wolf
Add "verific -import -flatten" and "verific -import -v"
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2017-07-22
Clifford Wolf
Add more SVA test cases for future Verific work
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2017-07-22
Clifford Wolf
Add "verific -import -k"
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2017-07-22
Clifford Wolf
Add error for cell output ports that are connected...
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2017-07-22
Clifford Wolf
Add some simple SVA test cases for future Verific work
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2017-07-22
Clifford Wolf
Improve docs for verific bindings, add simply sby example
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2017-07-21
Clifford Wolf
Fix handling of empty cell port assignments (i.e. ignor...
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2017-07-21
Clifford Wolf
Fix "read_blif -wideports" handling of cells with wide...
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2017-07-21
Clifford Wolf
Add a paragraph about pre-defined macros to read_verilo...
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2017-07-21
Clifford Wolf
Add verilator support to testbenches generated by yosys...
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2017-07-18
Clifford Wolf
Change intptr_t to uintptr_t in hashlib.h
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