yosys.git
2019-12-12 Eddie Hungabc9_map.v: fix Xilinx LUTRAM
2019-12-12 Eddie HungUpdate README.md :: abc_ -> abc9_
2019-12-11 Eddie HungFix bitwidth mismatch; suppresses iverilog warning
2019-12-11 David ShahMerge pull request #1564 from ZirconiumX/intel_housekeeping
2019-12-10 Dan Ravensloftsynth_intel: a10gx -> arria10gx
2019-12-10 Dan Ravensloftsynth_intel: cyclone10 -> cyclone10lp
2019-12-10 Eddie HungMerge pull request #1545 from YosysHQ/eddie/ice40_wrapc...
2019-12-09 Eddie Hungice40_opt to restore attributes/name when unwrapping
2019-12-09 Eddie Hungice40_wrapcarry -unwrap to preserve 'src' attribute
2019-12-09 Eddie Hungunmap $__ICE40_CARRY_WRAPPER in test
2019-12-09 Eddie Hung-unwrap to create $lut not SB_LUT4 for opt_lut
2019-12-09 Eddie HungSensitive to direct inst of $__ICE40_CARRY_WRAPPER...
2019-12-09 Eddie Hungice40_wrapcarry to really preserve attributes via ...
2019-12-07 Eddie HungMerge pull request #1555 from antmicro/fix-macc-xilinx...
2019-12-07 Eddie HungDrop keep=0 attributes on SB_CARRY
2019-12-06 Jan Kowalewskitests: arch: xilinx: Change order of arguments in macc.sh
2019-12-05 Clifford WolfMerge pull request #1551 from whitequark/manual-cell...
2019-12-05 Eddie HungMerge SB_CARRY+SB_LUT4's attributes when creating ...
2019-12-05 Eddie HungAdd WIP test for unwrapping $__ICE40_CARRY_WRAPPER
2019-12-04 whitequarkkernel: require \B_SIGNED=0 on $shl, $sshl, $shr, ...
2019-12-04 whitequarkmanual: document behavior of many comb cells more preci...
2019-12-04 Marcin Kościelnickixilinx: Add tristate buffer mapping. (#1528)
2019-12-04 Marcin Kościelnickiiopadmap: Refactor and fix tristate buffer mapping...
2019-12-04 Marcin Kościelnickixilinx: Add models for LUTRAM cells. (#1537)
2019-12-03 Eddie HungCheck SB_CARRY name also preserved
2019-12-03 Eddie Hung$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for...
2019-12-03 Eddie Hungice40_opt to ignore (* keep *) -ed cells
2019-12-03 Eddie Hungice40_wrapcarry to preserve SB_CARRY's attributes
2019-12-03 Eddie HungAdd testcase
2019-12-03 Clifford WolfMerge pull request #1524 from pepijndevos/gowindffinit
2019-12-03 Pepijn de Vosupdate test
2019-12-03 Pepijn de VosUse -match-init to not synth contradicting init values
2019-12-02 David ShahMerge pull request #1542 from YosysHQ/dave/abc9-loop-fix
2019-12-02 Clifford WolfMerge pull request #1539 from YosysHQ/mwk/ilang-bounds...
2019-12-01 David Shahabc9: Fix breaking of SCCs
2019-11-29 Miodrag MilanovićMerge pull request #1540 from YosysHQ/mwk/xilinx-bufpll
2019-11-29 Marcin Kościelnickixilinx: Add missing blackbox cell for BUFPLL.
2019-11-28 Eddie HungRevert "Fold loop"
2019-11-27 Marcin Kościelnickiread_ilang: do bounds checking on bit indices
2019-11-27 Eddie HungMerge pull request #1536 from YosysHQ/eddie/xilinx_dsp_...
2019-11-27 Clifford WolfMerge pull request #1501 from YosysHQ/dave/mem_copy_attr
2019-11-27 Clifford WolfMerge pull request #1534 from YosysHQ/mwk/opt_share-fix
2019-11-27 Eddie HungMerge pull request #1535 from YosysHQ/eddie/write_xaige...
2019-11-27 Eddie HungNo need for -abc9
2019-11-27 Marcin Kościelnickiopt_share: Fix handling of fine cells.
2019-11-27 Eddie Hunglatch -> box
2019-11-27 Eddie HungAdd citation
2019-11-27 Eddie HungCheck for either sign or zero extension for postAdd...
2019-11-27 Eddie HungRemove notes
2019-11-27 Eddie HungFold loop
2019-11-27 Eddie HungDo not sigmap keep bits inside write_xaiger
2019-11-27 Eddie Hungxaiger: do not promote output wires
2019-11-27 Eddie HungAdd testcase derived from fastfir_dynamictaps benchmark
2019-11-26 Marcin Kościelnickixilinx: Add simulation models for IOBUF and OBUFT.
2019-11-25 Marcin Kościelnickiclkbufmap: Add support for inverters in clock path.
2019-11-25 Marcin Kościelnickixilinx: Use INV instead of LUT1 when applicable
2019-11-25 Pepijn de Vosattempt to fix formatting
2019-11-25 Pepijn de Vosgowin: add and test dff init values
2019-11-23 Eddie HungMerge pull request #1520 from pietrmar/fix-1463
2019-11-23 Martin Pietrykacoolrunner2: remove spurious log_pop() call, fixes...
2019-11-22 Clifford WolfMerge pull request #1517 from YosysHQ/clifford/optmem
2019-11-22 Clifford WolfMerge pull request #1515 from YosysHQ/clifford/svastuff
2019-11-22 Clifford WolfAdd "opt_mem" pass
2019-11-22 Clifford WolfAdd Verific support for SVA nexttime properties
2019-11-22 Clifford WolfImprove handling of verific primitives in "verific...
2019-11-22 Clifford WolfAdd Verific SVA support for "always" properties
2019-11-22 Clifford WolfMerge pull request #1511 from YosysHQ/dave/always
2019-11-22 Marcin Kościelnickigowin: Remove show command from tests.
2019-11-22 Marcin Kościelnickigowin: Add missing .gitignore entries
2019-11-22 David ShahUpdate CHANGELOG and README
2019-11-21 David Shahsv: Add tests for SV always types
2019-11-21 David Shahproc_dlatch: Add error handling for incorrect always_...
2019-11-21 David Shahsv: Correct parsing of always_comb, always_ff and alway...
2019-11-20 Clifford WolfMerge pull request #1507 from YosysHQ/clifford/verificfixes
2019-11-20 Clifford WolfCorrectly treat empty modules as blackboxes in Verific
2019-11-20 Clifford WolfDo not rename VHDL entities to "entity(impl)" when...
2019-11-19 Clifford WolfMerge pull request #1449 from pepijndevos/gowin
2019-11-19 Pepijn de VosRemove dff init altogether
2019-11-19 Marcin KościelnickiFix #1462, #1480.
2019-11-19 Marcin Kościelnickixilinx: Add simulation models for MULT18X18* and DSP48A*.
2019-11-18 David Shahmemory_collect: Copy attr from RTLIL::Memory to cell
2019-11-18 Pepijn de Vosadd help for nowidelut and abc9 options
2019-11-18 Clifford WolfMerge pull request #1497 from YosysHQ/mwk/extract-fa-fix
2019-11-18 whitequarkMerge pull request #1494 from whitequark/write_verilog...
2019-11-18 Marcin KościelnickiFix #1496.
2019-11-18 whitequarkwrite_verilog: add -extmem option, to write split memor...
2019-11-17 Clifford WolfMerge pull request #1492 from YosysHQ/dave/wreduce...
2019-11-16 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-15 David Shahecp5: Use new autoname pass for better cell/net names
2019-11-14 David Shahwreduce: Don't trim zeros or sext when not matching...
2019-11-14 Clifford WolfMerge pull request #1490 from YosysHQ/clifford/autoname
2019-11-14 Clifford WolfMerge pull request #1444 from btut/feature/python_wrapp...
2019-11-14 Clifford WolfMerge pull request #1465 from YosysHQ/dave/ice40_timing_sim
2019-11-14 Clifford WolfMerge branch 'makaimann-label-bads-btor'
2019-11-14 Clifford WolfUse cell name for btor bad state props when it is a...
2019-11-14 Clifford WolfMerge branch 'label-bads-btor' of https://github.com...
2019-11-13 Clifford WolfAdd "autoname" pass and use it in "synth_ice40"
2019-11-13 whitequarkMerge pull request #1488 from whitequark/flowmap-fixes
2019-11-13 Clifford WolfMerge pull request #1486 from YosysHQ/clifford/fsmdetectfix
2019-11-12 Clifford WolfUpdate fsm_detect bugfix
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