2019-06-14 |
Eddie Hung | Revert "Cleanup/optimise toposort in write_xaiger" |
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2019-06-14 |
Eddie Hung | Update comment |
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2019-06-14 |
Eddie Hung | Check that whiteboxes are synthesisable |
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2019-06-14 |
Eddie Hung | Get rid of compiler warnings |
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2019-06-14 |
Eddie Hung | As per @daveshah1 remove async DFF timing from xilinx |
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2019-06-14 |
Eddie Hung | Cover __APPLE__ too for little to big endian |
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2019-06-14 |
Eddie Hung | Update abc9 -D doc |
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2019-06-14 |
Eddie Hung | Enable "abc9 -D <num>" for timing-driven synthesis |
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2019-06-14 |
Eddie Hung | Further cleanup based on @daveshah1 |
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2019-06-14 |
Eddie Hung | Resolve comments from @daveshah1 |
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2019-06-14 |
Eddie Hung | Add XC7_WIRE_DELAY macro to synth_xilinx.cc |
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2019-06-14 |
Eddie Hung | Update delays based on SymbiFlow/prjxray-db |
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2019-06-14 |
Eddie Hung | Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut} |
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2019-06-14 |
Eddie Hung | Comment out dist RAM boxing on ECP5 for now |
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2019-06-14 |
Eddie Hung | Remove WIP ABC9 flop support |
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2019-06-14 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig |
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2019-06-14 |
Eddie Hung | Make doc consistent |
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2019-06-14 |
Eddie Hung | Cleanup |
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2019-06-14 |
Eddie Hung | Merge branch 'xaig' of github.com:YosysHQ/yosys into... |
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2019-06-14 |
Eddie Hung | Merge pull request #1097 from YosysHQ/dave/xaig_ecp5 |
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2019-06-14 |
Eddie Hung | Cleanup |
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2019-06-14 |
Eddie Hung | Cleanup/optimise toposort in write_xaiger |
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2019-06-14 |
Eddie Hung | Remove extra semicolon |
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2019-06-14 |
Eddie Hung | Add TODO to parse_xaiger |
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2019-06-14 |
David Shah | ecp5: Add abc9 option |
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2019-06-14 |
Eddie Hung | Optimise some more |
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2019-06-13 |
Eddie Hung | Move ConstEvalAig to aigerparse.cc |
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2019-06-13 |
Eddie Hung | Fix name clash |
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2019-06-13 |
Eddie Hung | More slimming |
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2019-06-13 |
Eddie Hung | Add ConstEvalAig specialised for AIGs |
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2019-06-13 |
Eddie Hung | Update CHANGELOG with "synth -abc9" |
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2019-06-13 |
Eddie Hung | Fix LP SB_LUT4 timing |
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2019-06-13 |
Eddie Hung | More accurate CHANGELOG |
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2019-06-13 |
Serge Bazanski | Merge pull request #829 from abdelrahmanhosny/master |
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2019-06-12 |
Eddie Hung | Update CHANGELOG |
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2019-06-12 |
Eddie Hung | Rip out all non FPGA stuff from abc9 |
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2019-06-12 |
Eddie Hung | Fix spelling |
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2019-06-12 |
Eddie Hung | Revert "For 'stat' do not count modules with abc_box_id" |
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2019-06-12 |
Eddie Hung | Revert "Merge remote-tracking branch 'origin/eddie... |
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2019-06-12 |
Eddie Hung | Move neg-pol to pos-pol mapping from ff_map to cells_map.v |
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2019-06-12 |
Eddie Hung | Be more precise when connecting during ABC9 re-integration |
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2019-06-12 |
Eddie Hung | Remove unnecessary undriven_bits.insert |
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2019-06-12 |
Eddie Hung | Remove hacky wideports_split from abc9 |
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2019-06-12 |
Eddie Hung | Fix compile errors when #if 1 for debug |
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2019-06-12 |
Eddie Hung | parse_xaiger to cope with inouts |
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2019-06-12 |
Eddie Hung | write_xaiger to preserve POs even if driven by constant |
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2019-06-12 |
Eddie Hung | Add a couple more tests |
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2019-06-12 |
Eddie Hung | Do not call abc9 if no outputs |
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2019-06-12 |
Eddie Hung | More write_xaiger cleanup |
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2019-06-12 |
Eddie Hung | Cleanup write_xaiger |
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2019-06-12 |
Eddie Hung | Consistency |
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2019-06-12 |
Eddie Hung | Reduce diff with master |
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2019-06-12 |
Eddie Hung | Remove abc_flop{,_d} attributes from ice40/cells_sim.v |
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2019-06-12 |
Eddie Hung | Fix spacing |
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2019-06-12 |
Eddie Hung | Remove wide mux inference |
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2019-06-12 |
Eddie Hung | Merge branch 'xc7mux' into xaig |
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2019-06-12 |
Eddie Hung | Merge branch 'xc7mux' of github.com:YosysHQ/yosys into... |
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2019-06-12 |
Eddie Hung | Typo: wire delay is -W argument |
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2019-06-12 |
Eddie Hung | Revert "Merge remote-tracking branch 'origin/eddie... |
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2019-06-12 |
Eddie Hung | Revert "Merge remote-tracking branch 'origin/eddie... |
commit | commitdiff | tree |
2019-06-12 |
Eddie Hung | Revert "Merge remote-tracking branch 'origin/eddie... |
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2019-06-12 |
Eddie Hung | Merge remote-tracking branch 'origin/xc7mux' into xaig |
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2019-06-12 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig |
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2019-06-12 |
Eddie Hung | Retry "Add "-W' wire delay arg to abc9, use from synth_... |
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2019-06-12 |
Eddie Hung | Revert "Add "-W' wire delay arg to abc9, use from synth... |
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2019-06-12 |
Eddie Hung | Add "-W' wire delay arg to abc9, use from synth_xilinx |
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2019-06-11 |
Eddie Hung | Revert "Merge remote-tracking branch 'origin/eddie... |
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2019-06-11 |
Eddie Hung | Merge remote-tracking branch 'origin/eddie/shregmap_imp... |
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2019-06-11 |
Eddie Hung | Try way that doesn't involve creating a new wire |
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2019-06-11 |
Eddie Hung | Disable dist RAM boxes due to comb loop |
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2019-06-11 |
Eddie Hung | Remove #ifndef ABC |
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2019-06-10 |
Eddie Hung | Merge remote-tracking branch 'origin/eddie/shregmap_imp... |
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2019-06-10 |
Eddie Hung | If d_bit already in sigbit_chain_next, create extra... |
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2019-06-10 |
Eddie Hung | Add test |
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2019-06-10 |
Eddie Hung | Revert "Revert "Move ff_map back after ABC for shregmap"" |
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2019-06-10 |
Eddie Hung | Revert "Rename shregmap -tech xilinx -> xilinx_dynamic" |
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2019-06-10 |
Eddie Hung | Revert "shregmap -tech xilinx_dynamic to work -params... |
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2019-06-10 |
Eddie Hung | Revert "Refactor to ShregmapTechXilinx7Static" |
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2019-06-10 |
Eddie Hung | Revert "Add -tech xilinx_static" |
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2019-06-10 |
Eddie Hung | Revert "Continue support for ShregmapTechXilinx7Static" |
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2019-06-10 |
Eddie Hung | Revert "shregmap -tech xilinx_static to handle INIT" |
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2019-06-10 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xc7mux |
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2019-06-10 |
Eddie Hung | Add some more comments |
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2019-06-10 |
David Shah | Merge pull request #1082 from corecode/u4k |
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2019-06-10 |
Simon Schubert | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR... |
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2019-06-08 |
Clifford Wolf | Merge pull request #1078 from YosysHQ/eddie/muxcover_costs |
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2019-06-08 |
Eddie Hung | Update CHANGELOG |
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2019-06-07 |
Eddie Hung | Comment out muxpack (currently broken) |
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2019-06-07 |
Eddie Hung | Fine tune aigerparse |
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2019-06-07 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xc7mux |
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2019-06-07 |
Eddie Hung | Fix spacing from spaces to tabs |
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2019-06-07 |
Clifford Wolf | Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger |
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2019-06-07 |
Eddie Hung | Add read_aiger to CHANGELOG |
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2019-06-07 |
Eddie Hung | Fix spacing (entire file is wrong anyway, will fix... |
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2019-06-07 |
Eddie Hung | Remove unnecessary std::getline() for ASCII |
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2019-06-07 |
Eddie Hung | Test *.aag too, by using *.aig as reference |
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2019-06-07 |
Eddie Hung | Fix read_aiger -- create zero driver, fix init width... |
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2019-06-07 |
Eddie Hung | Use ABC to convert from AIGER to Verilog |
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2019-06-07 |
Eddie Hung | Use ABC to convert AIGER to Verilog, then sat against... |
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2019-06-07 |
Eddie Hung | Add symbols to AIGER test inputs for ABC |
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next |