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yosys.git
2022-02-07
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2022-02-06
Marcelina Kościelnicka
nexus: Fix arith_map CO signal.
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2022-02-03
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2022-02-02
Miodrag Milanović
Merge pull request #3183 from YosysHQ/micko/nto1mux
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2022-02-02
Miodrag Milanovic
Use bmux for NTO1MUX
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2022-02-02
Miodrag Milanović
Merge pull request #3182 from yrabbit/wip-doc2
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2022-02-02
YRabbit
Correct a typo in the manual
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2022-02-02
Scott Thibault
Update comment
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2022-02-02
Scott Thibault
Fix unextend method for signed constants
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2022-01-31
Miodrag Milanović
Merge pull request #3176 from higuoxing/fix-ref-manual
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2022-01-31
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2022-01-31
Marcelina Kościelnicka
verilog backend: Emit a `wire` for ports as well.
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2022-01-30
Xing GUO
Fix the help message of synth_quicklogic.
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2022-01-30
Marcelina Kościelnicka
opt_reduce: Add $bmux and $demux optimization patterns.
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2022-01-29
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2022-01-28
Marcelina Kościelnicka
Add $bmux and $demux cells.
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2022-01-28
Marcelina Kościelnicka
opt_dff: Don't mutate muxes while ModWalker is active.
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2022-01-28
Marcelina Kościelnicka
kernel/mem: Add read-first semantic emulation code.
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2022-01-28
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2022-01-27
Marcelina Kościelnicka
manual: Fix a custom pass example.
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2022-01-27
Marcelina Kościelnicka
memory_bram: Make use of new mem emulation functions...
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2022-01-27
Marcelina Kościelnicka
kernel/mem: Add functions to emulate read port enable...
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2022-01-27
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2022-01-26
Miodrag Milanović
change to windows-2019
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2022-01-20
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2022-01-19
gatecat
nexus: Fix BB sim model
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2022-01-19
Miodrag Milanovic
Removed dbits 8 since 9 will always be picked
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2022-01-19
Miodrag Milanović
Merge pull request #3120 from Icenowy/anlogic-bram
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2022-01-18
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2022-01-17
Miodrag Milanović
Merge pull request #3162 from YosysHQ/mmicko/windows_gu...
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2022-01-17
Miodrag Milanović
Update guidelines/Windows
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2022-01-17
N. Engelhardt
Merge pull request #3145 from nakengelhardt/advertise_s...
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2022-01-17
N. Engelhardt
mention distributions' package manager
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2022-01-17
Miodrag Milanović
Add info about VS build
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2022-01-12
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2022-01-11
Miodrag Milanovic
Forgot one
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2022-01-11
Miodrag Milanovic
Change url to https
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2022-01-11
Miodrag Milanovic
Next dev cycle
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2022-01-11
Miodrag Milanovic
Release version 0.13
yosys-0.13
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2022-01-11
Miodrag Milanovic
Update CHANGELOG
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2022-01-09
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2022-01-08
Zachary Snow
sv: auto add nosync to certain always_comb local vars
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2022-01-08
Zachary Snow
sv: fix size cast internal expression extension
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2022-01-05
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2022-01-04
Zachary Snow
logger: fix unmatched expected warnings and errors
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2022-01-04
Austin Seipp
opt_dff: fix sequence point copy paste bug
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2022-01-04
N. Engelhardt
mention tabby+oss cad suite in readme
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2022-01-04
gatecat
manual: Fix cell-stmt order
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2022-01-04
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2022-01-03
Zachary Snow
fix iverilog compatibility for new case expr tests
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2022-01-03
Zachary Snow
fixup verilog doubleslash test
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2022-01-03
Zachary Snow
sv: fix size cast clipping expression width
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2022-01-03
Miodrag Milanovic
Update manual
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2021-12-26
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2021-12-25
Catherine
Merge pull request #3127 from whitequark/cxxrtl-no...
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2021-12-25
Catherine
cxxrtl: don't reset elided wires with \init attribute.
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2021-12-22
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2021-12-21
Lofty
intel_alm: disable 256x40 M10K mode
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2021-12-21
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2021-12-20
Marcelina Kościelnicka
memory_share: Fix SAT-based sharing for wide ports.
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2021-12-19
github-actions...
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2021-12-18
Zachary Snow
fix width detection of array querying function in case...
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2021-12-17
Icenowy Zheng
anlogic: support BRAM mapping
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2021-12-17
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2021-12-16
Catherine
Merge pull request #3115 from whitequark/issue-3112
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2021-12-16
Catherine
Merge pull request #3114 from whitequark/issue-3113
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2021-12-16
Thomas Sailer
preprocessor: do not destroy double slash escaped ident...
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2021-12-15
Catherine
cxxrtl: demote wires not inlinable only in debug_eval...
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2021-12-15
Catherine
bugpoint: avoid infinite loop between -connections...
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2021-12-15
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2021-12-14
Catherine
Merge pull request #3111 from whitequark/issue-3110
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2021-12-14
Claire Xenia...
Hotfix for run_shell auto-detection
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2021-12-14
Catherine
Fix null pointer dereference after failing to extract...
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2021-12-14
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2021-12-13
Claire Xen
Merge pull request #3108 from YosysHQ/claire/verificdefs
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2021-12-13
Claire Xenia...
Add YOSYS to the implicitly defined verilog macros...
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2021-12-13
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2021-12-12
Marcelina Kościelnicka
Add clean_zerowidth pass, use it for Verilog output.
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2021-12-12
Catherine
Merge pull request #3105 from whitequark/cxxrtl-reset...
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2021-12-12
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2021-12-12
Marcelina Kościelnicka
Fix unused param warning with ENABLE_NDEBUG.
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2021-12-12
Marcelina Kościelnicka
rtlil: Dump empty connections when whole module is...
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2021-12-11
Catherine
cxxrtl: preserve interior memory pointers across reset.
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2021-12-11
Catherine
Merge pull request #3103 from whitequark/write_verilog...
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2021-12-11
whitequark
cxxrtl: use unique_ptr<value<>[]> to store memory contents.
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2021-12-11
whitequark
write_verilog: dump zero width sigspecs correctly.
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2021-12-11
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2021-12-10
Miodrag Milanović
Merge pull request #3102 from YosysHQ/claire/enumxz
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2021-12-10
Claire Xenia...
Fix verific import of enum values with x and/or z
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2021-12-10
Miodrag Milanović
Merge pull request #3097 from YosysHQ/modport
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2021-12-10
Claire Xen
Update verific.cc
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2021-12-10
Claire Xen
Merge pull request #3099 from YosysHQ/claire/readargs
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2021-12-09
Claire Xenia...
Fix the tests we just broke
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2021-12-09
Claire Xenia...
Added "yosys -r <topmodule>"
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2021-12-09
Claire Xenia...
Use "read" command to parse HDL files from Yosys comman...
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2021-12-09
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2021-12-08
Marcelina Kościelnicka
opt_mem_priority: Fix non-ascii char in help message.
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2021-12-08
Miodrag Milanovic
If direction NONE use that from first bit
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2021-12-04
github-actions...
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2021-12-03
Miodrag Milanovic
Next dev cycle
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