gram.git
2020-07-24 Jean THOMASFix code styling
2020-07-24 Jean THOMASRemoving superfluous variables in multiplexer
2020-07-24 Jean THOMASRemove commented test
2020-07-24 Jean THOMASFix code styling
2020-07-24 Jean THOMASFix AntiStarvation
2020-07-24 Jean THOMASUse the correct value for test depth
2020-07-23 Jean THOMASParametric test size, add delay option between write...
2020-07-23 Jean THOMASRevert to timings from LiteDRAM
2020-07-23 Jean THOMASFix code styling
2020-07-23 Jean THOMASUse clk pin definition from upstream nmigen-boards
2020-07-23 Jean THOMASUpdate nMigen version requirement
2020-07-23 Jean THOMASFix burstdet CSR code
2020-07-23 Jean THOMASFix platform code for simulation
2020-07-22 Jean THOMASRemove DQSPattern import
2020-07-22 Jean THOMASAdd notes regarding CI usage
2020-07-22 Jean THOMASHandle rdly customization
2020-07-22 Jean THOMASRemove unnecessary signal reset
2020-07-22 Jean THOMASRework burstdet CSR code
2020-07-22 Jean THOMASFix granularity and sel in UARTBridge
2020-07-22 Jean THOMASFix ECPIX585Platform to work with the latest commits...
2020-07-21 Jean THOMASRework CSR interface for PHY
2020-07-21 Jean THOMASUse 0x00BA0BAB instead of 0x12345678 for better readability
2020-07-21 Jean THOMASRemove commented DDR3 resource definition
2020-07-21 Jean THOMASFix write timings
2020-07-21 Jean THOMASReplace Switch with If statement, indentation fixup
2020-07-20 Jean THOMASRemove DQSPattern
2020-07-20 Jean THOMASApply changes from LiteDRAM#fa7d91a
2020-07-20 Jean THOMASFix code styling
2020-07-20 Jean THOMASAdding test for tXXDController
2020-07-20 Jean THOMASAdd simple test for DQSPattern
2020-07-20 Jean THOMASDisable SSH access for successful builds
2020-07-20 Jean THOMASSimplify parameters code for DQSPattern
2020-07-20 Jean THOMASRemove unused code (PHYPadsCombiner/PHYPadsReducer)
2020-07-20 Jean THOMASFix code styling
2020-07-20 Jean THOMASSet SEL when reading
2020-07-20 Jean THOMASRemove useless signal
2020-07-20 Jean THOMASUse PinsN when possible (fixes #27)
2020-07-20 Jean THOMASSimplify PHY read code
2020-07-17 Jean THOMASUse XDR for RAS#, CAS#, WE#, CLK_EN and ODT
2020-07-17 Jean THOMASCode cleaning in ECP5 PHY
2020-07-17 Jean THOMASUse XDR for ba pins
2020-07-17 Jean THOMASUse XDR for address pins
2020-07-17 Jean THOMASFix when there are multiple clocks
2020-07-17 Jean THOMASUse nMigen's XDR for DDR clk
2020-07-17 Jean THOMASRemove unused signal
2020-07-17 Jean THOMASFix code styling
2020-07-17 Jean THOMASRemove adaptation code
2020-07-17 Jean THOMASRemove get_port() function
2020-07-17 Jean THOMASAdd test for _AntiStarvation timer duration
2020-07-17 Jean THOMASFix code styling
2020-07-17 Jean THOMASUse the right domain
2020-07-17 Jean THOMASFix PHY issues
2020-07-17 Jean THOMASReduce delay between wishbone_write
2020-07-17 Jean THOMASFactor MRx setting code
2020-07-17 Jean THOMASLog DRAM commands
2020-07-17 Jean THOMASPut proc_rmdead after proc_mux
2020-07-17 Jean THOMASName each BankMachine instance to improve VCD output
2020-07-17 Jean THOMASFix CRG parameters
2020-07-17 Jean THOMASFix DQS_N errors
2020-07-17 Jean THOMASAdd more read transactions, add checks, ASAP
2020-07-17 Jean THOMASRemove event in ECP5DDRPHY
2020-07-17 Jean THOMASRemove comment
2020-07-16 Jean THOMASUse assertions in simsoc testbench
2020-07-16 Jean THOMASAdd logging and delays to the simulation to make it...
2020-07-16 Jean THOMASTweak yosys script
2020-07-16 Jean THOMASBackport modifications from example's CRG
2020-07-15 Jean THOMASWrite logic equivalences in a clearer way
2020-07-15 Jean THOMASMake Micron model read the mem_init.txt file
2020-07-15 Jean THOMASMake gram simulations faster
2020-07-15 Jean THOMASAdd initial memory content
2020-07-15 Jean THOMASAdd early code for RAM calibration
2020-07-15 Jean THOMASExpose DFII functions to other objects
2020-07-15 Jean THOMASIncrease UART bridge speed in simulation, decrease...
2020-07-15 Jean THOMASLog RAM signals
2020-07-15 Jean THOMASFix code styling
2020-07-15 Jean THOMASRemove arbiter from headless-ecpix5 example
2020-07-15 Jean THOMASUse random values for memtest
2020-07-13 Jean THOMASPer bytes error highlighting
2020-07-13 Jean THOMASMake _AddressSlicer an elaboratable
2020-07-13 Jean THOMASUpdate amount of tests
2020-07-13 Jean THOMASRemove unnecessary arbiter
2020-07-13 Jean THOMASFix timings in libgram
2020-07-13 Jean THOMASReduce POR duration
2020-07-13 Jean THOMASFix gearing and UART speed
2020-07-13 Jean THOMASAdd additional opt+clean and print stats
2020-07-13 Jean THOMASMake full use of the native port
2020-07-13 Jean THOMASFix gearing
2020-07-13 Jean THOMASFix FakePHY bank emulation
2020-07-13 Jean THOMASRemove UnusedElaboratable warning
2020-07-10 Jean THOMASFix memtest tests (missing parenthesis)
2020-07-10 Jean THOMASAdd more memory tests
2020-07-10 Jean THOMASRemove unused files
2020-07-10 Jean THOMASPut every gram component in the dramsync clock domain
2020-07-10 Jean THOMASUse clock freq from platform
2020-07-10 Jean THOMASUse R02 platform file
2020-07-10 Jean THOMASExternalize CRG
2020-07-10 Jean THOMASFix DDR3 module parameter
2020-07-10 Jean THOMASFix code styling
2020-07-10 Jean THOMASAdd a name to timing_checker submodule
2020-07-10 Jean THOMASRework headless client interface
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