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gram.git
2020-07-24
Jean THOMAS
Fix code styling
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2020-07-24
Jean THOMAS
Removing superfluous variables in multiplexer
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2020-07-24
Jean THOMAS
Remove commented test
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2020-07-24
Jean THOMAS
Fix code styling
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2020-07-24
Jean THOMAS
Fix AntiStarvation
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2020-07-24
Jean THOMAS
Use the correct value for test depth
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2020-07-23
Jean THOMAS
Parametric test size, add delay option between write...
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2020-07-23
Jean THOMAS
Revert to timings from LiteDRAM
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2020-07-23
Jean THOMAS
Fix code styling
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2020-07-23
Jean THOMAS
Use clk pin definition from upstream nmigen-boards
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2020-07-23
Jean THOMAS
Update nMigen version requirement
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2020-07-23
Jean THOMAS
Fix burstdet CSR code
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2020-07-23
Jean THOMAS
Fix platform code for simulation
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2020-07-22
Jean THOMAS
Remove DQSPattern import
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2020-07-22
Jean THOMAS
Add notes regarding CI usage
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2020-07-22
Jean THOMAS
Handle rdly customization
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2020-07-22
Jean THOMAS
Remove unnecessary signal reset
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2020-07-22
Jean THOMAS
Rework burstdet CSR code
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2020-07-22
Jean THOMAS
Fix granularity and sel in UARTBridge
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2020-07-22
Jean THOMAS
Fix ECPIX585Platform to work with the latest commits...
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2020-07-21
Jean THOMAS
Rework CSR interface for PHY
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2020-07-21
Jean THOMAS
Use 0x00BA0BAB instead of 0x12345678 for better readability
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2020-07-21
Jean THOMAS
Remove commented DDR3 resource definition
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2020-07-21
Jean THOMAS
Fix write timings
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2020-07-21
Jean THOMAS
Replace Switch with If statement, indentation fixup
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2020-07-20
Jean THOMAS
Remove DQSPattern
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2020-07-20
Jean THOMAS
Apply changes from LiteDRAM#fa7d91a
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2020-07-20
Jean THOMAS
Fix code styling
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2020-07-20
Jean THOMAS
Adding test for tXXDController
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2020-07-20
Jean THOMAS
Add simple test for DQSPattern
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2020-07-20
Jean THOMAS
Disable SSH access for successful builds
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2020-07-20
Jean THOMAS
Simplify parameters code for DQSPattern
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2020-07-20
Jean THOMAS
Remove unused code (PHYPadsCombiner/PHYPadsReducer)
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2020-07-20
Jean THOMAS
Fix code styling
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2020-07-20
Jean THOMAS
Set SEL when reading
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2020-07-20
Jean THOMAS
Remove useless signal
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2020-07-20
Jean THOMAS
Use PinsN when possible (fixes #27)
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2020-07-20
Jean THOMAS
Simplify PHY read code
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2020-07-17
Jean THOMAS
Use XDR for RAS#, CAS#, WE#, CLK_EN and ODT
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2020-07-17
Jean THOMAS
Code cleaning in ECP5 PHY
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2020-07-17
Jean THOMAS
Use XDR for ba pins
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2020-07-17
Jean THOMAS
Use XDR for address pins
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2020-07-17
Jean THOMAS
Fix when there are multiple clocks
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2020-07-17
Jean THOMAS
Use nMigen's XDR for DDR clk
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2020-07-17
Jean THOMAS
Remove unused signal
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2020-07-17
Jean THOMAS
Fix code styling
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2020-07-17
Jean THOMAS
Remove adaptation code
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2020-07-17
Jean THOMAS
Remove get_port() function
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2020-07-17
Jean THOMAS
Add test for _AntiStarvation timer duration
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2020-07-17
Jean THOMAS
Fix code styling
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2020-07-17
Jean THOMAS
Use the right domain
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2020-07-17
Jean THOMAS
Fix PHY issues
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2020-07-17
Jean THOMAS
Reduce delay between wishbone_write
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2020-07-17
Jean THOMAS
Factor MRx setting code
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2020-07-17
Jean THOMAS
Log DRAM commands
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2020-07-17
Jean THOMAS
Put proc_rmdead after proc_mux
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2020-07-17
Jean THOMAS
Name each BankMachine instance to improve VCD output
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2020-07-17
Jean THOMAS
Fix CRG parameters
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2020-07-17
Jean THOMAS
Fix DQS_N errors
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2020-07-17
Jean THOMAS
Add more read transactions, add checks, ASAP
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2020-07-17
Jean THOMAS
Remove event in ECP5DDRPHY
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2020-07-17
Jean THOMAS
Remove comment
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2020-07-16
Jean THOMAS
Use assertions in simsoc testbench
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2020-07-16
Jean THOMAS
Add logging and delays to the simulation to make it...
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2020-07-16
Jean THOMAS
Tweak yosys script
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2020-07-16
Jean THOMAS
Backport modifications from example's CRG
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2020-07-15
Jean THOMAS
Write logic equivalences in a clearer way
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2020-07-15
Jean THOMAS
Make Micron model read the mem_init.txt file
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2020-07-15
Jean THOMAS
Make gram simulations faster
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2020-07-15
Jean THOMAS
Add initial memory content
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2020-07-15
Jean THOMAS
Add early code for RAM calibration
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2020-07-15
Jean THOMAS
Expose DFII functions to other objects
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2020-07-15
Jean THOMAS
Increase UART bridge speed in simulation, decrease...
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2020-07-15
Jean THOMAS
Log RAM signals
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2020-07-15
Jean THOMAS
Fix code styling
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2020-07-15
Jean THOMAS
Remove arbiter from headless-ecpix5 example
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2020-07-15
Jean THOMAS
Use random values for memtest
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2020-07-13
Jean THOMAS
Per bytes error highlighting
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2020-07-13
Jean THOMAS
Make _AddressSlicer an elaboratable
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2020-07-13
Jean THOMAS
Update amount of tests
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2020-07-13
Jean THOMAS
Remove unnecessary arbiter
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2020-07-13
Jean THOMAS
Fix timings in libgram
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2020-07-13
Jean THOMAS
Reduce POR duration
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2020-07-13
Jean THOMAS
Fix gearing and UART speed
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2020-07-13
Jean THOMAS
Add additional opt+clean and print stats
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2020-07-13
Jean THOMAS
Make full use of the native port
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2020-07-13
Jean THOMAS
Fix gearing
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2020-07-13
Jean THOMAS
Fix FakePHY bank emulation
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2020-07-13
Jean THOMAS
Remove UnusedElaboratable warning
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2020-07-10
Jean THOMAS
Fix memtest tests (missing parenthesis)
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2020-07-10
Jean THOMAS
Add more memory tests
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2020-07-10
Jean THOMAS
Remove unused files
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2020-07-10
Jean THOMAS
Put every gram component in the dramsync clock domain
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2020-07-10
Jean THOMAS
Use clock freq from platform
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2020-07-10
Jean THOMAS
Use R02 platform file
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2020-07-10
Jean THOMAS
Externalize CRG
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2020-07-10
Jean THOMAS
Fix DDR3 module parameter
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2020-07-10
Jean THOMAS
Fix code styling
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2020-07-10
Jean THOMAS
Add a name to timing_checker submodule
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2020-07-10
Jean THOMAS
Rework headless client interface
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