yosys.git
2019-06-13 Eddie HungMore accurate CHANGELOG
2019-06-12 Eddie HungUpdate CHANGELOG
2019-06-12 Eddie HungRip out all non FPGA stuff from abc9
2019-06-12 Eddie HungFix spelling
2019-06-12 Eddie HungRevert "For 'stat' do not count modules with abc_box_id"
2019-06-12 Eddie HungRevert "Merge remote-tracking branch 'origin/eddie...
2019-06-12 Eddie HungMove neg-pol to pos-pol mapping from ff_map to cells_map.v
2019-06-12 Eddie HungBe more precise when connecting during ABC9 re-integration
2019-06-12 Eddie HungRemove unnecessary undriven_bits.insert
2019-06-12 Eddie HungRemove hacky wideports_split from abc9
2019-06-12 Eddie HungFix compile errors when #if 1 for debug
2019-06-12 Eddie Hungparse_xaiger to cope with inouts
2019-06-12 Eddie Hungwrite_xaiger to preserve POs even if driven by constant
2019-06-12 Eddie HungAdd a couple more tests
2019-06-12 Eddie HungDo not call abc9 if no outputs
2019-06-12 Eddie HungMore write_xaiger cleanup
2019-06-12 Eddie HungCleanup write_xaiger
2019-06-12 Eddie HungConsistency
2019-06-12 Eddie HungReduce diff with master
2019-06-12 Eddie HungRemove abc_flop{,_d} attributes from ice40/cells_sim.v
2019-06-12 Eddie HungFix spacing
2019-06-12 Eddie HungRemove wide mux inference
2019-06-12 Eddie HungMerge branch 'xc7mux' into xaig
2019-06-12 Eddie HungMerge branch 'xc7mux' of github.com:YosysHQ/yosys into...
2019-06-12 Eddie HungTypo: wire delay is -W argument
2019-06-12 Eddie HungRevert "Merge remote-tracking branch 'origin/eddie...
2019-06-12 Eddie HungRevert "Merge remote-tracking branch 'origin/eddie...
2019-06-12 Eddie HungRevert "Merge remote-tracking branch 'origin/eddie...
2019-06-12 Eddie HungMerge remote-tracking branch 'origin/xc7mux' into xaig
2019-06-12 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-12 Eddie HungRetry "Add "-W' wire delay arg to abc9, use from synth_...
2019-06-12 Eddie HungRevert "Add "-W' wire delay arg to abc9, use from synth...
2019-06-12 Eddie HungAdd "-W' wire delay arg to abc9, use from synth_xilinx
2019-06-11 Eddie HungRevert "Merge remote-tracking branch 'origin/eddie...
2019-06-11 Eddie HungMerge remote-tracking branch 'origin/eddie/shregmap_imp...
2019-06-11 Eddie HungTry way that doesn't involve creating a new wire
2019-06-11 Eddie HungDisable dist RAM boxes due to comb loop
2019-06-11 Eddie HungRemove #ifndef ABC
2019-06-10 Eddie HungMerge remote-tracking branch 'origin/eddie/shregmap_imp...
2019-06-10 Eddie HungIf d_bit already in sigbit_chain_next, create extra...
2019-06-10 Eddie HungAdd test
2019-06-10 Eddie HungRevert "Revert "Move ff_map back after ABC for shregmap""
2019-06-10 Eddie HungRevert "Rename shregmap -tech xilinx -> xilinx_dynamic"
2019-06-10 Eddie HungRevert "shregmap -tech xilinx_dynamic to work -params...
2019-06-10 Eddie HungRevert "Refactor to ShregmapTechXilinx7Static"
2019-06-10 Eddie HungRevert "Add -tech xilinx_static"
2019-06-10 Eddie HungRevert "Continue support for ShregmapTechXilinx7Static"
2019-06-10 Eddie HungRevert "shregmap -tech xilinx_static to handle INIT"
2019-06-10 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-06-10 Eddie HungAdd some more comments
2019-06-10 David ShahMerge pull request #1082 from corecode/u4k
2019-06-10 Simon Schubertice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR...
2019-06-08 Clifford WolfMerge pull request #1078 from YosysHQ/eddie/muxcover_costs
2019-06-08 Eddie HungUpdate CHANGELOG
2019-06-07 Eddie HungComment out muxpack (currently broken)
2019-06-07 Eddie HungFine tune aigerparse
2019-06-07 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-06-07 Eddie HungFix spacing from spaces to tabs
2019-06-07 Clifford WolfMerge pull request #1079 from YosysHQ/eddie/fix_read_aiger
2019-06-07 Eddie HungAdd read_aiger to CHANGELOG
2019-06-07 Eddie HungFix spacing (entire file is wrong anyway, will fix...
2019-06-07 Eddie HungRemove unnecessary std::getline() for ASCII
2019-06-07 Eddie HungTest *.aag too, by using *.aig as reference
2019-06-07 Eddie HungFix read_aiger -- create zero driver, fix init width...
2019-06-07 Eddie HungUse ABC to convert from AIGER to Verilog
2019-06-07 Eddie HungUse ABC to convert AIGER to Verilog, then sat against...
2019-06-07 Eddie HungAdd symbols to AIGER test inputs for ABC
2019-06-07 Eddie HungAllow muxcover costs to be changed
2019-06-07 Eddie HungAllow muxcover costs to be changed
2019-06-07 Clifford WolfMerge pull request #1077 from YosysHQ/clifford/pr983
2019-06-07 Clifford WolfRename implicit_ports.sv test to implicit_ports.v
2019-06-07 Clifford WolfFixes and cleanups in AST_TECALL handling
2019-06-07 Clifford WolfMerge branch 'pr_elab_sys_tasks' of https://github...
2019-06-07 Clifford WolfMerge branch 'tux3-implicit_named_connection'
2019-06-07 Clifford WolfMerge pull request #1076 from thasti/centos7-build-fix
2019-06-07 Clifford WolfCleanup tux3-implicit_named_connection
2019-06-07 Clifford WolfMerge branch 'implicit_named_connection' of https:...
2019-06-07 Stefan Biereigelremove boost/log/exceptions.hpp from wrapper generator
2019-06-06 Eddie Hung$__XILINX_MUX_ -> $__XILINX_SHIFTX
2019-06-06 Eddie HungFix muxcover and its techmapping
2019-06-06 Eddie HungRun muxpack and muxcover in synth_xilinx
2019-06-06 Eddie HungRemove abc_flop attributes for now
2019-06-06 Eddie HungMerge remote-tracking branch 'origin/eddie/muxpack...
2019-06-06 Eddie HungFix and test for balanced case
2019-06-06 Eddie HungMerge remote-tracking branch 'origin/eddie/muxpack...
2019-06-06 Eddie HungFix warnings
2019-06-06 Eddie HungSupport cascading $pmux.A with $mux.A and $mux.B
2019-06-06 Eddie HungMore cleanup
2019-06-06 Eddie HungFix spacing
2019-06-06 Eddie HungNon chain user check using next_sig
2019-06-06 Eddie HungAdd non exclusive test
2019-06-06 Eddie HungMove muxpack from passes/techmap to passes/opt
2019-06-06 Eddie HungUpdate doc
2019-06-06 Eddie HungAdd to CHANGELOG
2019-06-06 Eddie HungOne more and tidy up
2019-06-06 Eddie HungAdd a few more special case tests
2019-06-06 Eddie HungAdd tests, fix for !=
2019-06-06 Eddie HungMissing file
2019-06-06 Eddie HungInitial adaptation of muxpack from shregmap
2019-06-06 tux3SystemVerilog support for implicit named port connections
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