yosys.git
2019-06-18 Eddie HungMerge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-18 Eddie HungUpdate LUT7/8 delays to take account for [ABC]OUTMUX...
2019-06-17 Eddie HungMerge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-17 Eddie Hung&scorr before &sweep, remove &retime as recommended
2019-06-17 Eddie HungMerge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-17 Eddie HungCopy not move parameters/attributes
2019-06-17 Eddie HungMerge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-17 Eddie HungFix leak removing cells during ABC integration; also...
2019-06-17 Eddie HungMerge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-17 Eddie HungTry -W 300
2019-06-17 Eddie HungRe-enable &dc2
2019-06-16 Eddie HungTry -W 300
2019-06-16 Eddie HungMerge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-16 Eddie HungCleanup
2019-06-15 Eddie HungMerge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-15 Eddie HungFix upper XC7 LUT[78] delays to use I[01] -> O delay...
2019-06-14 Eddie HungMerge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-14 Eddie HungLeave breadcrumb behind
2019-06-14 Eddie HungRemove redundant condition
2019-06-14 Eddie HungRevert "Cleanup/optimise toposort in write_xaiger"
2019-06-14 Eddie HungRevert "Cleanup/optimise toposort in write_xaiger"
2019-06-14 Eddie HungMerge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-14 Eddie HungUpdate comment
2019-06-14 Eddie HungCheck that whiteboxes are synthesisable
2019-06-14 Eddie HungGet rid of compiler warnings
2019-06-14 Eddie HungUpdate CHANGELOG
2019-06-14 Eddie HungRevert "Remove wide mux inference"
2019-06-14 Eddie HungMerge branch 'xaig' into xc7mux
2019-06-14 Eddie HungAs per @daveshah1 remove async DFF timing from xilinx
2019-06-14 Eddie HungCover __APPLE__ too for little to big endian
2019-06-14 Eddie HungUpdate abc9 -D doc
2019-06-14 Eddie HungEnable "abc9 -D <num>" for timing-driven synthesis
2019-06-14 Eddie HungFurther cleanup based on @daveshah1
2019-06-14 Eddie HungResolve comments from @daveshah1
2019-06-14 Eddie HungAdd XC7_WIRE_DELAY macro to synth_xilinx.cc
2019-06-14 Eddie HungUpdate delays based on SymbiFlow/prjxray-db
2019-06-14 Eddie HungRename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
2019-06-14 Eddie HungComment out dist RAM boxing on ECP5 for now
2019-06-14 Eddie HungRemove WIP ABC9 flop support
2019-06-14 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-14 Eddie HungMake doc consistent
2019-06-14 Eddie HungCleanup
2019-06-14 Eddie HungMerge branch 'xaig' of github.com:YosysHQ/yosys into...
2019-06-14 Eddie HungMerge pull request #1097 from YosysHQ/dave/xaig_ecp5
2019-06-14 Eddie HungCleanup
2019-06-14 Eddie HungCleanup/optimise toposort in write_xaiger
2019-06-14 Eddie HungRemove extra semicolon
2019-06-14 Eddie HungAdd TODO to parse_xaiger
2019-06-14 David Shahecp5: Add abc9 option
2019-06-14 Eddie HungOptimise some more
2019-06-13 Eddie HungMove ConstEvalAig to aigerparse.cc
2019-06-13 Eddie HungFix name clash
2019-06-13 Eddie HungMore slimming
2019-06-13 Eddie HungAdd ConstEvalAig specialised for AIGs
2019-06-13 Eddie HungUpdate CHANGELOG with "synth -abc9"
2019-06-13 Eddie HungFix LP SB_LUT4 timing
2019-06-13 Eddie HungMore accurate CHANGELOG
2019-06-13 Serge BazanskiMerge pull request #829 from abdelrahmanhosny/master
2019-06-12 Eddie HungUpdate CHANGELOG
2019-06-12 Eddie HungRip out all non FPGA stuff from abc9
2019-06-12 Eddie HungFix spelling
2019-06-12 Eddie HungRevert "For 'stat' do not count modules with abc_box_id"
2019-06-12 Eddie HungRevert "Merge remote-tracking branch 'origin/eddie...
2019-06-12 Eddie HungMove neg-pol to pos-pol mapping from ff_map to cells_map.v
2019-06-12 Eddie HungBe more precise when connecting during ABC9 re-integration
2019-06-12 Eddie HungRemove unnecessary undriven_bits.insert
2019-06-12 Eddie HungRemove hacky wideports_split from abc9
2019-06-12 Eddie HungFix compile errors when #if 1 for debug
2019-06-12 Eddie Hungparse_xaiger to cope with inouts
2019-06-12 Eddie Hungwrite_xaiger to preserve POs even if driven by constant
2019-06-12 Eddie HungAdd a couple more tests
2019-06-12 Eddie HungDo not call abc9 if no outputs
2019-06-12 Eddie HungMore write_xaiger cleanup
2019-06-12 Eddie HungCleanup write_xaiger
2019-06-12 Eddie HungConsistency
2019-06-12 Eddie HungReduce diff with master
2019-06-12 Eddie HungRemove abc_flop{,_d} attributes from ice40/cells_sim.v
2019-06-12 Eddie HungFix spacing
2019-06-12 Eddie HungRemove wide mux inference
2019-06-12 Eddie HungMerge branch 'xc7mux' into xaig
2019-06-12 Eddie HungMerge branch 'xc7mux' of github.com:YosysHQ/yosys into...
2019-06-12 Eddie HungTypo: wire delay is -W argument
2019-06-12 Eddie HungRevert "Merge remote-tracking branch 'origin/eddie...
2019-06-12 Eddie HungRevert "Merge remote-tracking branch 'origin/eddie...
2019-06-12 Eddie HungRevert "Merge remote-tracking branch 'origin/eddie...
2019-06-12 Eddie HungMerge remote-tracking branch 'origin/xc7mux' into xaig
2019-06-12 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-12 Eddie HungRetry "Add "-W' wire delay arg to abc9, use from synth_...
2019-06-12 Eddie HungRevert "Add "-W' wire delay arg to abc9, use from synth...
2019-06-12 Eddie HungAdd "-W' wire delay arg to abc9, use from synth_xilinx
2019-06-11 Eddie HungRevert "Merge remote-tracking branch 'origin/eddie...
2019-06-11 Eddie HungMerge remote-tracking branch 'origin/eddie/shregmap_imp...
2019-06-11 Eddie HungTry way that doesn't involve creating a new wire
2019-06-11 Eddie HungDisable dist RAM boxes due to comb loop
2019-06-11 Eddie HungRemove #ifndef ABC
2019-06-10 Eddie HungMerge remote-tracking branch 'origin/eddie/shregmap_imp...
2019-06-10 Eddie HungIf d_bit already in sigbit_chain_next, create extra...
2019-06-10 Eddie HungAdd test
2019-06-10 Eddie HungRevert "Revert "Move ff_map back after ABC for shregmap""
2019-06-10 Eddie HungRevert "Rename shregmap -tech xilinx -> xilinx_dynamic"
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