2020-02-01 |
whitequark | _unused: extract must-use logic from hdl.ir. |
commit | commitdiff | tree |
2020-01-31 |
whitequark | hdl.dsl: add missing case width check for Enum values. |
commit | commitdiff | tree |
2020-01-31 |
whitequark | README: clarify relationship to Migen. |
commit | commitdiff | tree |
2020-01-31 |
whitequark | hdl.dsl: make `if m.{If,Elif,Else}(...)` a syntax error. |
commit | commitdiff | tree |
2020-01-31 |
whitequark | back.rtlil: don't emit wires for empty signals. |
commit | commitdiff | tree |
2020-01-31 |
Mike Walters | vendor.lattice_ecp5: support internal oscillator (OSCG). |
commit | commitdiff | tree |
2020-01-31 |
Jaro Habiger | build.dsl: allow strings to be used as connector numbers. |
commit | commitdiff | tree |
2020-01-31 |
Sylvain Munaut | vendor.lattice_{ice40,ecp5}: Support .il (RTLIL) files... |
commit | commitdiff | tree |
2020-01-27 |
whitequark | Update README. |
commit | commitdiff | tree |
2020-01-18 |
whitequark | hdl.ir: resolve hierarchy conflicts before creating... |
commit | commitdiff | tree |
2020-01-17 |
whitequark | hdl.xfrm: transform drivers as well in DomainRenamer. |
commit | commitdiff | tree |
2020-01-12 |
whitequark | Remove everything deprecated in nmigen 0.1. |
commit | commitdiff | tree |
2020-01-11 |
Staf Verhaegen | Signal: allow to use integral Enum for reset value. |
commit | commitdiff | tree |
2020-01-09 |
schwigi | vendor.intel: fix output enable width for XDR=0 case. |
commit | commitdiff | tree |
2020-01-07 |
Alain Péteut | build.run: fix indentation. |
commit | commitdiff | tree |
2020-01-01 |
whitequark | back.rtlil: do not consider unreachable array elements... |
commit | commitdiff | tree |
2019-12-15 |
whitequark | hdl.mem: fix src_loc_at in ReadPort, WritePort. |
commit | commitdiff | tree |
2019-12-04 |
Marcin Kościelnicki | hdl.ast: Fix width for unary minus operator on signed... |
commit | commitdiff | tree |
2019-12-02 |
whitequark | back.pysim: fix miscompilation of Signal(unsigned)... |
commit | commitdiff | tree |
2019-12-02 |
whitequark | hdl.ast: actually remove simulator commands. |
commit | commitdiff | tree |
2019-12-01 |
Dan Ravensloft | vendor.intel: silence meaningless warnings in nMigen... |
commit | commitdiff | tree |
2019-11-28 |
whitequark | back.pysim: redesign the simulator. |
commit | commitdiff | tree |
2019-11-27 |
whitequark | back.rtlil: infer bit width for instance parameters. |
commit | commitdiff | tree |
2019-11-26 |
whitequark | hdl.ir: for instance ports, prioritize defs over uses. |
commit | commitdiff | tree |
2019-11-18 |
Jean-François... | vendor.xilinx_*: Set IOB attribute on cels instead... |
commit | commitdiff | tree |
2019-11-18 |
whitequark | back.rtlil: extend shorter operand of a binop when... |
commit | commitdiff | tree |
2019-11-15 |
whitequark | build.plat: in Platform.add_file(), allow adding exact... |
commit | commitdiff | tree |
2019-11-15 |
whitequark | test: add tests for build.plat.Platform.add_file. |
commit | commitdiff | tree |
2019-11-09 |
whitequark | hdl.rec: fix Record.like() being called through a subclass. v0.1 |
commit | commitdiff | tree |
2019-11-09 |
Staf Verhaegen | hdl.rec: make Record(name=) keyword-only. |
commit | commitdiff | tree |
2019-11-07 |
whitequark | hdl.ir: lower domains before resolving hierarchy conflicts. |
commit | commitdiff | tree |
2019-11-02 |
whitequark | Improve .gitignore. |
commit | commitdiff | tree |
2019-10-28 |
whitequark | back.verilog: remove $verilog_initial_trigger after... |
commit | commitdiff | tree |
2019-10-26 |
whitequark | test: use `#nmigen:` magic comment instead of monkey... |
commit | commitdiff | tree |
2019-10-26 |
whitequark | hdl.ir: allow disabling UnusedElaboratable warning... |
commit | commitdiff | tree |
2019-10-26 |
whitequark | back.rtlil: avoid exponential behavior when legalizing... |
commit | commitdiff | tree |
2019-10-26 |
whitequark | back.rtlil: fix lowering of Part() on LHS to account... |
commit | commitdiff | tree |
2019-10-26 |
whitequark | hdl.ast: simplify {bit,word}_select with constant offset. |
commit | commitdiff | tree |
2019-10-21 |
whitequark | Explicitly restrict prelude imports. |
commit | commitdiff | tree |
2019-10-17 |
whitequark | compat.fhdl.specials: fix argument parsing compatibility. |
commit | commitdiff | tree |
2019-10-16 |
whitequark | lib.io: use keyword-only arguments in Pin(). |
commit | commitdiff | tree |
2019-10-16 |
whitequark | setup: fix commit 5198d99b. |
commit | commitdiff | tree |
2019-10-16 |
Sebastien Bourdeauducq | verilog: fix yosys version error message |
commit | commitdiff | tree |
2019-10-16 |
whitequark | back.verilog: fix Yosys version check. |
commit | commitdiff | tree |
2019-10-15 |
whitequark | setup: don't append local version for tags. v0.1rc1 |
commit | commitdiff | tree |
2019-10-14 |
whitequark | vendor.lattice_ice40: fix commit 88649def. |
commit | commitdiff | tree |
2019-10-13 |
whitequark | vendor.lattice_{ice40,ecp5}: fix typo. |
commit | commitdiff | tree |
2019-10-13 |
whitequark | vendor.lattice_ice40: use pcf files instead of pre... |
commit | commitdiff | tree |
2019-10-13 |
whitequark | build.plat: batch files use EQU, not EQ. |
commit | commitdiff | tree |
2019-10-13 |
whitequark | {,_}tools→{,_}utils |
commit | commitdiff | tree |
2019-10-13 |
whitequark | vendor.lattice_{ice40,ecp5}: emit Verilog as well,... |
commit | commitdiff | tree |
2019-10-13 |
whitequark | build.plat: fold emit_prelude() into emit_commands(). |
commit | commitdiff | tree |
2019-10-13 |
Emily | Refactor build script toolchain lookups. |
commit | commitdiff | tree |
2019-10-13 |
whitequark | hdl.ir: allow ClockSignal and ResetSignal in ports. |
commit | commitdiff | tree |
2019-10-13 |
whitequark | hdl.ir: cast instance port connections to Values. |
commit | commitdiff | tree |
2019-10-13 |
whitequark | compat.fhdl.decorators: improve backwards compatibility. |
commit | commitdiff | tree |
2019-10-13 |
whitequark | compat.fhdl.bitcontainer: update Value.wrap call. |
commit | commitdiff | tree |
2019-10-12 |
whitequark | doc: bring COMPAT_SUMMARY up to date. |
commit | commitdiff | tree |
2019-10-12 |
whitequark | compat.genlib.fsm: add migration warning. |
commit | commitdiff | tree |
2019-10-12 |
whitequark | compat.fhdl.decorators: add migration warnings. |
commit | commitdiff | tree |
2019-10-12 |
whitequark | hdl.ast: rename Slice.end back to Slice.stop. |
commit | commitdiff | tree |
2019-10-12 |
whitequark | compat.fhdl.structure: remove SPECIAL_* constants. |
commit | commitdiff | tree |
2019-10-12 |
whitequark | _tools: extract most utility methods to a private package. |
commit | commitdiff | tree |
2019-10-12 |
Jean-François... | back.rtlil: fix DeprecationWarning. NFC. |
commit | commitdiff | tree |
2019-10-11 |
whitequark | Rename remaining `wrap` methods to `cast`. |
commit | commitdiff | tree |
2019-10-11 |
whitequark | hdl.ast: deprecate shapes like `(1, True)` in favor... |
commit | commitdiff | tree |
2019-10-11 |
whitequark | hdl.ast: deprecate Signal.{range,enum}. |
commit | commitdiff | tree |
2019-10-11 |
whitequark | hdl.ast: add an explicit Shape class, included in prelude. |
commit | commitdiff | tree |
2019-10-11 |
whitequark | Consistently use {!r}, not '{!r}' in diagnostics. |
commit | commitdiff | tree |
2019-10-11 |
whitequark | hdl.ast: Operator.{op→operator} |
commit | commitdiff | tree |
2019-10-11 |
whitequark | hdl.ast: simplify enum handling. |
commit | commitdiff | tree |
2019-10-11 |
whitequark | hdl.ast: Value.{wrap→cast} |
commit | commitdiff | tree |
2019-10-10 |
whitequark | vendor.xilinx_ultrascale: new supported family. |
commit | commitdiff | tree |
2019-10-10 |
whitequark | xilinx_7series: add grade platform property. |
commit | commitdiff | tree |
2019-10-10 |
whitequark | vendor.lattice_machxo2: new supported family. |
commit | commitdiff | tree |
2019-10-10 |
whitequark | vendor: yosys is a required tool for all Verilog-based... |
commit | commitdiff | tree |
2019-10-10 |
whitequark | README: add device support matrix. |
commit | commitdiff | tree |
2019-10-10 |
whitequark | vendor.intel: add Quartus support. |
commit | commitdiff | tree |
2019-10-09 |
whitequark | examples: update blinky, add some explanatory text... |
commit | commitdiff | tree |
2019-10-09 |
whitequark | build.plat: elaborate result of create_missing_domain... |
commit | commitdiff | tree |
2019-10-09 |
whitequark | build.plat: don't create default sync domain as reset... |
commit | commitdiff | tree |
2019-10-09 |
whitequark | build.plat,vendor: always synchronize reset in default... |
commit | commitdiff | tree |
2019-10-06 |
whitequark | back.rtlil: don't crash legalizing values with no branches. |
commit | commitdiff | tree |
2019-10-04 |
whitequark | back.rtlil: avoid unsoundness for division by zero. |
commit | commitdiff | tree |
2019-10-04 |
whitequark | hdl.ast: prohibit signed divisors. |
commit | commitdiff | tree |
2019-10-03 |
whitequark | build.dsl: accept Pins(invert=True). |
commit | commitdiff | tree |
2019-10-02 |
whitequark | hdl.ast: don't crash on Mux(<bool>, ...). |
commit | commitdiff | tree |
2019-10-02 |
whitequark | back.rtlil: don't cache wires for legalized switch... |
commit | commitdiff | tree |
2019-10-02 |
whitequark | back.rtlil: sign of rhs and lhs of ${sshr,sshl,pow... |
commit | commitdiff | tree |
2019-10-02 |
whitequark | back.rtlil: it is not necessary to match binop operand... |
commit | commitdiff | tree |
2019-09-30 |
Jean-François... | rpc: add public Records as module ports. |
commit | commitdiff | tree |
2019-09-30 |
whitequark | rpc: add support for Yosys RPC protocol. |
commit | commitdiff | tree |
2019-09-28 |
whitequark | hdl.ast: actually implement the // operator. |
commit | commitdiff | tree |
2019-09-28 |
whitequark | hdl.dsl: add a diagnostic for `m.d.submodules += ...`. |
commit | commitdiff | tree |
2019-09-28 |
whitequark | hdl.mem: remove WritePort(priority=) argument. |
commit | commitdiff | tree |
2019-09-24 |
whitequark | back.rtlil: fix handling of certain nested arrays. |
commit | commitdiff | tree |
2019-09-24 |
whitequark | build.plat: strip internal attributes from Verilog... |
commit | commitdiff | tree |
2019-09-24 |
whitequark | build.plat,lib.cdc,vendor: unify platform related diagn... |
commit | commitdiff | tree |
2019-09-24 |
whitequark | lib.cdc: specify maximum input delay in seconds. |
commit | commitdiff | tree |
2019-09-24 |
whitequark | vendor.xilinx_spartan_3_6: explain why ASYNC_REG is... |
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