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yosys.git
2014-03-06 Clifford WolfStrictly zero-extend unsigned A-inputs of shift operations commit | commitdiff | tree
2014-03-05 Clifford WolfSwitched to EZMINISAT_SIMPSOLVER as default SAT solver commit | commitdiff | tree
2014-03-05 Clifford WolfInclude id2ast pointers when dumping AST commit | commitdiff | tree
2014-03-05 Clifford WolfFixed merging of compatible wire decls in AST frontend commit | commitdiff | tree
2014-03-05 Clifford WolfBugfix in recursive AST simplification commit | commitdiff | tree
2014-03-03 Clifford Wolffixed freduce for Minisat::SimpSolver: use frozen_literal() commit | commitdiff | tree
2014-03-03 Clifford WolfezSAT: Added frozen_literal() API commit | commitdiff | tree
2014-03-03 Clifford WolfezSAT: Fixed handling of eliminated Literals, added... commit | commitdiff | tree
2014-03-01 Clifford WolfAdded ezSAT::eliminated API to help the SAT solver... commit | commitdiff | tree
2014-03-01 Clifford WolfezSAT bugfix: don't call virtual methods in base class... commit | commitdiff | tree
2014-03-01 Clifford WolfRemoved ezSAT::assumed() API commit | commitdiff | tree
2014-03-01 Clifford WolfRemoved ezSAT built-in brute-froce solver commit | commitdiff | tree
2014-03-01 Clifford WolfFixed vhdl2verilog temp dir name commit | commitdiff | tree
2014-03-01 Clifford WolfFixed vhdl2verilog help message commit | commitdiff | tree
2014-02-27 Clifford WolfFixed const folding of $bu0 cells commit | commitdiff | tree
2014-02-26 Clifford WolfFixed bit-extending in $mux argument (use $bu0 instead... commit | commitdiff | tree
2014-02-26 Clifford WolfAdded support for $bu0 to SatGen commit | commitdiff | tree
2014-02-24 Clifford WolfDon't blow up constants unneccessarily in Verilog frontend commit | commitdiff | tree
2014-02-23 Clifford WolfAdded support for Minisat::SimpSolver + ezSAT frezze... commit | commitdiff | tree
2014-02-23 Clifford WolfFixed small memory leak in Pass::call() commit | commitdiff | tree
2014-02-22 Clifford WolfFixed bug in generation of undefs for $memwr MUXes commit | commitdiff | tree
2014-02-22 Clifford WolfFixed bug (typo) in passes/opt/opt_const.cc commit | commitdiff | tree
2014-02-22 Clifford WolfAdded $lut support to blif backend (by user eddiehung... commit | commitdiff | tree
2014-02-22 Clifford WolfAdded ezMiniSat EZMINISAT_INCREMENTAL compile-time... commit | commitdiff | tree
2014-02-22 Clifford WolfMade MiniSat solver backend configurable in ezminisat.h commit | commitdiff | tree
2014-02-21 Clifford WolfAdded workaround for vhdl-style edge triggers from... commit | commitdiff | tree
2014-02-21 Clifford WolfAdded vhdl2verilog commit | commitdiff | tree
2014-02-21 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-21 Clifford WolfBetter handling of nameDef and nameRef in edif backend commit | commitdiff | tree
2014-02-21 Clifford WolfFixed instantiating multi-bit ports in edif backend commit | commitdiff | tree
2014-02-21 Clifford WolfUse private namespace in mem_simple_4x1_map commit | commitdiff | tree
2014-02-21 Clifford WolfAdded tests/techmap/mem_simple_4x1 commit | commitdiff | tree
2014-02-21 Clifford WolfRenamed "write_blif -subckt" to "write_blif -icells... commit | commitdiff | tree
2014-02-21 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-20 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-20 Clifford WolfAdded _TECHMAP_REPLACE_ feature to techmap commit | commitdiff | tree
2014-02-20 Clifford WolfAdded "extract -ignore_parameters" and "extract -ignore... commit | commitdiff | tree
2014-02-20 Clifford WolfAdded "extract -map %<design_name>" commit | commitdiff | tree
2014-02-20 Clifford WolfAdded "design -push" and "design -pop" commit | commitdiff | tree
2014-02-20 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-20 Clifford WolfAdded connwrappers command commit | commitdiff | tree
2014-02-20 Clifford WolfCleanups in handling of read_verilog -defer and -icells commit | commitdiff | tree
2014-02-20 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-19 Clifford WolfAdded vcd2txt.pl and txt2tikztiming.py (tests/tools... commit | commitdiff | tree
2014-02-18 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys commit | commitdiff | tree
2014-02-18 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-18 Clifford WolfAdded techmap support for _TECHMAP_CONNMAP_*_ commit | commitdiff | tree
2014-02-18 Clifford WolfAdded "sat -dump_cnf" commit | commitdiff | tree
2014-02-18 Clifford WolfCoding style corrections in SatHelper::dump_model_to_vcd() commit | commitdiff | tree
2014-02-18 Clifford WolfImproved non-verbose ezSAT::printDIMACS() format commit | commitdiff | tree
2014-02-18 Clifford WolfAdded "sat -initsteps" commit | commitdiff | tree
2014-02-17 Clifford WolfAdded Verilog support for "`default_nettype none" commit | commitdiff | tree
2014-02-17 Clifford WolfRenamed "sat -dump_fail_to_vcd" to "sat -dump_vcd"... commit | commitdiff | tree
2014-02-17 Andrew ZonenbergAdded "-dump_fail_to_vcd" argument to SAT solver commit | commitdiff | tree
2014-02-17 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-17 Clifford WolfBetter preserve wires when flattening (in comparison... commit | commitdiff | tree
2014-02-16 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-16 Clifford WolfAdded some additional checks to techmap commit | commitdiff | tree
2014-02-16 Clifford WolfAdded CONSTMSK and CONSTVAL feature to techmap commit | commitdiff | tree
2014-02-16 Clifford WolfFixed handling of "keep" attribute on wires in opt_clean commit | commitdiff | tree
2014-02-16 Clifford WolfAdded a warning note about error reporting to read_veri... commit | commitdiff | tree
2014-02-16 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-16 Clifford WolfFixed use of selection in splitnets command commit | commitdiff | tree
2014-02-16 Clifford WolfAdded recursion support to techmap commit | commitdiff | tree
2014-02-16 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-16 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-02-16 Clifford WolfImproved support for constant functions commit | commitdiff | tree
2014-02-15 Clifford WolfNow we are in Yoys 0.2.0+ development commit | commitdiff | tree
2014-02-15 Clifford WolfTagging Yoys 0.2.0 yosys-0.2.0 commit | commitdiff | tree
2014-02-15 Clifford WolfAdded != support for relational select pattern commit | commitdiff | tree
2014-02-15 Clifford WolfAdded iopadmap -bits commit | commitdiff | tree
2014-02-15 Clifford WolfAdded ff and latch support to read_liberty commit | commitdiff | tree
2014-02-15 Clifford WolfBugfix in expression parser of read_liberty commit | commitdiff | tree
2014-02-15 Clifford WolfFixed dfflibmap for cell libraries with no set-reset-ff commit | commitdiff | tree
2014-02-15 Clifford WolfCorrectly convert constants to RTLIL (fixed undef handling) commit | commitdiff | tree
2014-02-15 Clifford WolfAdded frontend (-f) option to autotest.sh commit | commitdiff | tree
2014-02-15 Clifford WolfFixed opt_const handling of double invert with non... commit | commitdiff | tree
2014-02-15 Clifford WolfAdded liberty frontend commit | commitdiff | tree
2014-02-14 Clifford WolfBe more conservative with new const-function code commit | commitdiff | tree
2014-02-14 Clifford WolfAdded support for FOR loops in function calls in parameters commit | commitdiff | tree
2014-02-14 Clifford WolfCreated basic support for function calls in parameter... commit | commitdiff | tree
2014-02-14 Clifford WolfAdded abc -keepff option commit | commitdiff | tree
2014-02-13 Clifford Wolfupdated default ABC command strings commit | commitdiff | tree
2014-02-13 Clifford WolfUpdated ABC commit | commitdiff | tree
2014-02-13 Clifford WolfImplemented read_verilog -defer commit | commitdiff | tree
2014-02-13 Clifford WolfRemoved double blanks in ABC default command sequences commit | commitdiff | tree
2014-02-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys commit | commitdiff | tree
2014-02-13 Clifford WolfUpdated ABC and some related changes commit | commitdiff | tree
2014-02-12 Clifford WolfMerge pull request #26 from ahmedirfan1983/btor commit | commitdiff | tree
2014-02-12 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys commit | commitdiff | tree
2014-02-12 Clifford WolfAdded support for functions returning integer commit | commitdiff | tree
2014-02-12 Ahmed Irfanmodified btor synthesis script for correct use of splic... commit | commitdiff | tree
2014-02-12 Clifford WolfDisabled "abc -dff" in "make test" for now (waiting... commit | commitdiff | tree
2014-02-12 Clifford WolfUpdated ABC to rev e97a6e1d59b9 commit | commitdiff | tree
2014-02-11 Clifford Wolfrenamed ilang "scope error" to "ilang error" commit | commitdiff | tree
2014-02-11 Ahmed Irfandisabling splice command in the script commit | commitdiff | tree
2014-02-11 Ahmed Irfanregister output corrected commit | commitdiff | tree
2014-02-11 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... commit | commitdiff | tree
2014-02-11 Ahmed Irfanadded concat and slice cell translation commit | commitdiff | tree
2014-02-11 Clifford WolfMore Makefile cleanups commit | commitdiff | tree
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